Patents by Inventor Cheng-Yeh Huang
Cheng-Yeh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210384301Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a semiconductor strip structure over a semiconductor substrate. The semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, and the spacing region is an undoped region. The method includes performing an implantation process over the first doped region and the spacing region to convert a first upper portion of the first doped region and a second upper portion of the spacing region into a continuous disorder region. The method includes forming a metal-semiconductor compound layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region after the implantation process.Type: ApplicationFiled: August 23, 2021Publication date: December 9, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
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Patent number: 11101354Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.Type: GrantFiled: August 3, 2020Date of Patent: August 24, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
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Patent number: 10957762Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.Type: GrantFiled: May 19, 2020Date of Patent: March 23, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
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Patent number: 10892365Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.Type: GrantFiled: February 14, 2020Date of Patent: January 12, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
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Publication number: 20200365696Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.Type: ApplicationFiled: August 3, 2020Publication date: November 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
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Publication number: 20200279917Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.Type: ApplicationFiled: May 19, 2020Publication date: September 3, 2020Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
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Patent number: 10734489Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.Type: GrantFiled: November 2, 2018Date of Patent: August 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
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Patent number: 10700163Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.Type: GrantFiled: November 18, 2018Date of Patent: June 30, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
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Publication number: 20200194058Abstract: The present invention provides a static random access memory (SRAM), the SRAM includes a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern at least includes a first gate structure, a second gate structure and a third gate structure, arranged along a first direction, wherein the second gate structure and the third gate structure are parallel to the first gate structure, and a gap is disposed between the second gate structure and the third gate structure, and wherein the first gate structure is composed of a first elongated structure, a second elongated structure and a curved structure disposed between the first elongated structure and the second elongated structure, and wherein the curved structure is aligned with the gap along a second direction, and an interconnection contact structure disposed between the first gate structure and the second gate structure, and arranged along the first direction.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Inventors: Te-Chang Hsu, Cheng-Pu Chiu, Chun-Jen Huang, Cheng-Yeh Huang, Che-Hsien Lin, Yao-Jhan Wang
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Publication number: 20200185525Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.Type: ApplicationFiled: February 14, 2020Publication date: June 11, 2020Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
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Publication number: 20200127089Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.Type: ApplicationFiled: November 18, 2018Publication date: April 23, 2020Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
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Publication number: 20200105933Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.Type: ApplicationFiled: October 16, 2018Publication date: April 2, 2020Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
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Patent number: 10608113Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.Type: GrantFiled: October 16, 2018Date of Patent: March 31, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
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Publication number: 20200044035Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.Type: ApplicationFiled: November 2, 2018Publication date: February 6, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
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Patent number: 9746465Abstract: A magnetic bead-based digital microfluidic immunoanalysis device and a method thereof are provided, which includes a lower plate, an upper plate disposed above the lower plate, a separating structure therebetween and a magnet disposed on the upper plate or the lower plate. The lower plate includes a first electrode layer including a plurality of channel electrodes with different sizes. A droplet containing few magnetic beads is adapted to be disposed on the lower plate and corresponding to the channel electrodes. The magnet attracts the magnetic beads to approach to the smaller one of the channel electrodes though a magnetic force, and when a voltage is applied to the first electrode layer, the droplet is divided to a detection portion with the magnetic beads and a waste-liquid portion without the magnetic beads respectively corresponding to the smaller one and the larger one of the channel electrodes through a dual-direction electrowetting-on-dielectric force.Type: GrantFiled: June 15, 2015Date of Patent: August 29, 2017Assignee: National Chiao Tung UniversityInventors: Wensyang Hsu, Cheng-Yeh Huang, Po-Yen Tsai, Po-Huai Shih, Shih-Kang Fan, Da-Jeng Yao, Cheng-Hsien Liu, Hong-Yuan Huang
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Publication number: 20160274098Abstract: A magnetic bead-based digital microfluidic immunoanalysis device and a method thereof are provided, which includes a lower plate, an upper plate disposed above the lower plate, a separating structure therebetween and a magnet disposed on the upper plate or the lower plate. The lower plate includes a first electrode layer including a plurality of channel electrodes with different sizes. A droplet containing few magnetic beads is adapted to be disposed on the lower plate and corresponding to the channel electrodes. The magnet attracts the magnetic beads to approach to the smaller one of the channel electrodes though a magnetic force, and when a voltage is applied to the first electrode layer, the droplet is divided to a detection portion with the magnetic beads and a waste-liquid portion without the magnetic beads respectively corresponding to the smaller one and the larger one of the channel electrodes through a dual-direction electrowetting-on-dielectric force.Type: ApplicationFiled: June 15, 2015Publication date: September 22, 2016Inventors: Wensyang Hsu, Cheng-Yeh Huang, Po-Yen Tsai, Po-Huai Shih, Shih-Kang Fan, Da-Jeng Yao, Cheng-Hsien Liu, Hong-Yuan Huang