Patents by Inventor Cheng-Yeh Huang

Cheng-Yeh Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200365696
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region and extends over the isolation structure, the semiconductor strip structure has a first doped region and a spacing region connected to the first doped region, the first doped region extends across the first active region, the spacing region is over the isolation structure, and the spacing region is an undoped region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to continuously cover the first doped region and the spacing region.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
  • Patent number: 10790414
    Abstract: A light emitting diode includes an N-type semiconductor layer, a P-type semiconductor layer, and a light emitting layer. The P-type semiconductor layer is located on the N-type semiconductor layer. The light emitting layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The N-type semiconductor layer has a first region and a second region connected to each other. The first region is overlapped with the light emitting layer and the P-type semiconductor layer in a first direction. The second region is not overlapped with the light emitting layer and the P-type semiconductor layer in the first direction. A sheet resistance of the P-type semiconductor layer is smaller than a sheet resistance of the N-type semiconductor layer.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 29, 2020
    Assignee: Au Optronics Corporation
    Inventors: Pu-Jung Huang, Pin-Miao Liu, Cheng-Yeh Tsai, Chen-Chi Lin
  • Publication number: 20200279917
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Patent number: 10734489
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Cheng-Yeh Huang, Chin-Nan Chang, Chih-Ming Lee, Chi-Yen Lin
  • Patent number: 10700163
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Grant
    Filed: November 18, 2018
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200194058
    Abstract: The present invention provides a static random access memory (SRAM), the SRAM includes a substrate, a SRAM pattern disposed on the substrate, wherein the SRAM pattern at least includes a first gate structure, a second gate structure and a third gate structure, arranged along a first direction, wherein the second gate structure and the third gate structure are parallel to the first gate structure, and a gap is disposed between the second gate structure and the third gate structure, and wherein the first gate structure is composed of a first elongated structure, a second elongated structure and a curved structure disposed between the first elongated structure and the second elongated structure, and wherein the curved structure is aligned with the gap along a second direction, and an interconnection contact structure disposed between the first gate structure and the second gate structure, and arranged along the first direction.
    Type: Application
    Filed: December 12, 2018
    Publication date: June 18, 2020
    Inventors: Te-Chang Hsu, Cheng-Pu Chiu, Chun-Jen Huang, Cheng-Yeh Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Publication number: 20200185415
    Abstract: A pixel structure including a first light-emitting diode element, a second light-emitting diode element and a first interconnection pattern is provided. The first interconnection pattern is disposed on and electrically connected to a first electrode of the first light-emitting diode element and a first electrode of the second light-emitting diode element. The first interconnection pattern is configured to be electrically connected to a drive element. The first interconnection pattern includes a first main portion and a second main portion. The first main portion extending in a first direction is disposed on the first electrode of the first light-emitting diode element. The second main portion extending in a second direction and connected to the first main portion is disposed on the first electrode of the second light-emitting diode element. The first direction and the second direction are crossed.
    Type: Application
    Filed: October 7, 2019
    Publication date: June 11, 2020
    Applicant: Au Optronics Corporation
    Inventors: Pu-Jung Huang, Pin-Miao Liu, Cheng-Yeh Tsai
  • Publication number: 20200185525
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Application
    Filed: February 14, 2020
    Publication date: June 11, 2020
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10644181
    Abstract: A photovoltaic module is provided, and a cell set thereof includes a first cell, a second cell, and a conductive connection element. In the first cell, a first semiconductor stack has a first surface, a second surface, and a first side surface. A first electrode is disposed on the first surface. A second electrode is disposed on the second surface. In the second cell, a second semiconductor stack has a third surface, a fourth surface, and a second side surface. A third electrode is disposed on the third surface. A fourth electrode is disposed on the fourth surface. The conductive connection element connects the first electrode with a part of a first insulation layer on the second surface, and connects the third electrode with a part of a second insulation layer on the fourth surface.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Ping Huang, Shang-Yeh Wen, Cheng-Yu Peng
  • Publication number: 20200127089
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor substrate with gate structures formed thereon is provided. A source/drain region is formed in the semiconductor substrate and formed between the gate structures. A dielectric layer is formed on the source/drain region and located between the gate structures. An opening penetrating the dielectric layer on the source/drain region is formed. A lower portion of a first conductive structure is formed in the opening. A dielectric spacer is formed on the lower portion and on an inner wall of the opening. An upper portion of the first conductive structure is formed in the opening and on the lower portion. The dielectric spacer surrounds the upper portion of the first conductive structure. The first conductive structure is formed by two steps for forming the dielectric spacer surrounding the upper portion and improving the electrical performance of the semiconductor device.
    Type: Application
    Filed: November 18, 2018
    Publication date: April 23, 2020
    Inventors: Te-Chang Hsu, Che-Hsien Lin, Cheng-Yeh Huang, Chun-Jen Huang, Yu-Chih Su, Yao-Jhan Wang
  • Publication number: 20200105933
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Application
    Filed: October 16, 2018
    Publication date: April 2, 2020
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Patent number: 10608113
    Abstract: A semiconductor structure includes a semiconductor substrate, at least a silicon germanium (SiGe) epitaxial region disposed in the semiconductor substrate, and a contact structure disposed on the SiGe epitaxial region. The contact structure includes a titanium nitride (TiN) barrier layer and a metal layer surrounded by the TiN barrier layer. A crystalline titanium germanosilicide stressor layer is disposed in the SiGe epitaxial region and between the TiN barrier layer and the SiGe epitaxial region.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: March 31, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Yeh Huang, Te-Chang Hsu, Chun-Jen Huang, Che-Hsien Lin, Yao-Jhan Wang
  • Publication number: 20200044035
    Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.
    Type: Application
    Filed: November 2, 2018
    Publication date: February 6, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gulbagh SINGH, Cheng-Yeh HUANG, Chin-Nan CHANG, Chih-Ming LEE, Chi-Yen LIN
  • Publication number: 20190393382
    Abstract: A light emitting diode includes an N-type semiconductor layer, a P-type semiconductor layer, and a light emitting layer. The P-type semiconductor layer is located on the N-type semiconductor layer. The light emitting layer is located between the N-type semiconductor layer and the P-type semiconductor layer. The N-type semiconductor layer has a first region and a second region connected to each other. The first region is overlapped with the light emitting layer and the P-type semiconductor layer in a first direction. The second region is not overlapped with the light emitting layer and the P-type semiconductor layer in the first direction. A sheet resistance of the P-type semiconductor layer is smaller than a sheet resistance of the N-type semiconductor layer.
    Type: Application
    Filed: May 17, 2019
    Publication date: December 26, 2019
    Applicant: Au Optronics Corporation
    Inventors: Pu-Jung Huang, Pin-Miao Liu, Cheng-Yeh Tsai, Chen-Chi Lin
  • Patent number: 9746465
    Abstract: A magnetic bead-based digital microfluidic immunoanalysis device and a method thereof are provided, which includes a lower plate, an upper plate disposed above the lower plate, a separating structure therebetween and a magnet disposed on the upper plate or the lower plate. The lower plate includes a first electrode layer including a plurality of channel electrodes with different sizes. A droplet containing few magnetic beads is adapted to be disposed on the lower plate and corresponding to the channel electrodes. The magnet attracts the magnetic beads to approach to the smaller one of the channel electrodes though a magnetic force, and when a voltage is applied to the first electrode layer, the droplet is divided to a detection portion with the magnetic beads and a waste-liquid portion without the magnetic beads respectively corresponding to the smaller one and the larger one of the channel electrodes through a dual-direction electrowetting-on-dielectric force.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 29, 2017
    Assignee: National Chiao Tung University
    Inventors: Wensyang Hsu, Cheng-Yeh Huang, Po-Yen Tsai, Po-Huai Shih, Shih-Kang Fan, Da-Jeng Yao, Cheng-Hsien Liu, Hong-Yuan Huang
  • Publication number: 20160274098
    Abstract: A magnetic bead-based digital microfluidic immunoanalysis device and a method thereof are provided, which includes a lower plate, an upper plate disposed above the lower plate, a separating structure therebetween and a magnet disposed on the upper plate or the lower plate. The lower plate includes a first electrode layer including a plurality of channel electrodes with different sizes. A droplet containing few magnetic beads is adapted to be disposed on the lower plate and corresponding to the channel electrodes. The magnet attracts the magnetic beads to approach to the smaller one of the channel electrodes though a magnetic force, and when a voltage is applied to the first electrode layer, the droplet is divided to a detection portion with the magnetic beads and a waste-liquid portion without the magnetic beads respectively corresponding to the smaller one and the larger one of the channel electrodes through a dual-direction electrowetting-on-dielectric force.
    Type: Application
    Filed: June 15, 2015
    Publication date: September 22, 2016
    Inventors: Wensyang Hsu, Cheng-Yeh Huang, Po-Yen Tsai, Po-Huai Shih, Shih-Kang Fan, Da-Jeng Yao, Cheng-Hsien Liu, Hong-Yuan Huang