Patents by Inventor Cheng-Yen Hsieh
Cheng-Yen Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12374599Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: GrantFiled: January 17, 2024Date of Patent: July 29, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Publication number: 20250232832Abstract: Embodiments of the disclosure provide a solution for a protein language model. A method includes: obtaining a sequence representation of a protein comprising a plurality of amino acid residues, the sequence representation characterizing an amino acid sequence of the protein; determining, by a language model, a predicted discrete structure representation based on the sequence representation, wherein the predicted discrete structure representation comprises a plurality of bit sequences corresponding to the plurality of amino acid residues respectively, a bit sequence of the plurality of bit sequences represents a predicted local structure of a corresponding amino acid residue; and generating a target structure of the protein based on the predicted discrete structure representation.Type: ApplicationFiled: April 1, 2025Publication date: July 17, 2025Inventors: Cheng-Yen Hsieh, Xinyou Wang, Dongyu Xue, Fei Ye, Zaixiang Zheng, Quanquan Gu
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Publication number: 20240153843Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Publication number: 20240145421Abstract: Provided are a passivation layer for forming a semiconductor bonding structure, a sputtering target making the same, a semiconductor bonding structure and a semiconductor bonding process. The passivation layer is formed on a bonding substrate by sputtering the sputtering target; the passivation layer and the sputtering target comprise a first metal, a second metal or a combination thereof. The bonding substrate comprises a third metal. Based on a total atom number of the surface of the passivation layer, O content of the surface of the passivation layer is less than 30 at %; the third metal content of the surface of the passivation layer is less than or equal to 10 at %. The passivation layer has a polycrystalline structure. The semiconductor bonding structure sequentially comprises a first bonding substrate, a bonding layer and a second bonding substrate: the bonding layer is mainly formed by the passivation layer and the third metal.Type: ApplicationFiled: October 27, 2023Publication date: May 2, 2024Inventors: Kuan-Neng CHEN, Zhong-Jie HONG, Chih-I CHO, Ming-Wei WENG, Chih-Han CHEN, Chiao-Yen WANG, Ying-Chan HUNG, Hong-Yi WU, CHENG-YEN HSIEH
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Patent number: 11915994Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: GrantFiled: August 12, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Publication number: 20230051881Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: ApplicationFiled: August 12, 2021Publication date: February 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Patent number: 11545438Abstract: A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.Type: GrantFiled: November 6, 2020Date of Patent: January 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chun-Hui Yu, Ping-Kang Huang, Sao-Ling Chiu, Yi-Jhang Wang
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Publication number: 20220336362Abstract: A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.Type: ApplicationFiled: July 5, 2022Publication date: October 20, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chun-Hui Yu, Ping-Kang Huang, Sao-Ling Chiu, Yi-Jhang Wang
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Publication number: 20210202389Abstract: A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.Type: ApplicationFiled: November 6, 2020Publication date: July 1, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chun-Hui Yu, Ping-Kang Huang, Sao-Ling Chiu, Yi-Jhang Wang
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Patent number: 10867892Abstract: A semiconductor structure includes a first die including a first surface and a second surface opposite to the first surface; a first molding surrounding the first die; and a first redistribution layer (RDL) disposed over the second surface of the first die and the first molding, and including a first dielectric layer, a first interconnect structure surrounded by the first dielectric layer, and a cooling mechanism disposed within the first dielectric layer, wherein the cooling mechanism includes a first conductive member, a second conductive member disposed opposite to the first conductive member, a first thermoelectric member and a second thermoelectric member adjacent to the first thermoelectric member; and wherein the first thermoelectric member and the second thermoelectric member extend substantially in parallel to the second surface of the first die and extend between the first conductive member and the second conductive member.Type: GrantFiled: August 22, 2019Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Horng Chang, Cheng-Yen Hsieh