Abstract: The invention provides a configurable memory system including an interface layer, an overlay application layer, and a memory relocatable layer. The interface layer has a physical memory attribute module and a physical memory protection module. The interface layer manages memory attributes and memory security. The overlay application layer is coupled to the interface layer and executes an exception handler process to check if an overlay exception has occurred. The memory relocatable layer, coupled to the interface layer and the overlay application layer, having a plurality of resident service program within a first memory space, an overlay physical region within a second memory space, and a plurality of overlay virtual regions having application processes within a third memory space. The application processes of one of the overlay virtual regions is determined to be executed by the PMA module and is copied from the overlay virtual region to the overlay physical region by a processor.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

Abstract: This invention discloses a display panel including a first substrate, light emitting elements, a touch sensing structure and a conductive layer. The light emitting elements are disposed on the first substrate. The touch sensing structure is disposed on the first substrate and on a side away from a light emitting surface of the light emitting elements. The conductive layer is disposed between the light emitting elements and the first substrate and includes contacts or at least a portion of the touch sensing structure, and the light emitting elements and the contacts are electrically connected.

Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.

Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

Abstract: An apparatus and a method for video frame rotation are provided. The apparatus includes a synchronous dynamic random access memory (SDRAM) and a video rotation circuit. The video rotation circuit is coupled to the SDRAM. The video rotation circuit sequentially writes a plurality of pixels of a video frame into the SDRAM in a row-by-row scanning manner. The video rotation circuit divides a plurality of columns of the video frame into a plurality of column sets, so as to divide each of the rows of the video frame into a plurality of sub-rows. The video rotation circuit performs an internal column-set scanning for each of the column sets in a column-set-by-column-set manner, so as to discretely read the sub-rows from the SDRAM.

Abstract: Smart glasses and a method for recognizing and prompting a face are provided. The smart glasses store a database recording a plurality of profile information and business card information thereof. In the method, an image located in the field of view of the smart glasses is captured by an image capturing unit and at least one face appearing in the image is recognized. Facial features of each of the recognized faces are compared with those of the profile information in the database to find the profile information matching the facial features. In particular, if profile information matching the facial features is found, business card information corresponding to the profile information is displayed on a display unit; if profile information matching the facial features is not found, the business card information of a business card appearing in the image is recognized to associate the business card information with the recognized face.

Abstract: Smart glasses and a method for recognizing and prompting a face are provided. The smart glasses store a database recording a plurality of profile information and business card information thereof. In the method, an image located in the field of view of the smart glasses is captured by an image capturing unit and at least one face appearing in the image is recognized. Facial features of each of the recognized faces are compared with those of the profile information in the database to find the profile information matching the facial features. In particular, if profile information matching the facial features is found, business card information corresponding to the profile information is displayed on a display unit; if profile information matching the facial features is not found, the business card information of a business card appearing in the image is recognized to associate the business card information with the recognized face.

Abstract: A briefing system, a wearable device, and a note presentation method for briefing are provided. The briefing system includes a control unit, a projection unit and a wearable device. The projection unit is adapted to connect to the control unit in a wired/wireless manner and display a briefing content. The wearable device is adapted to communicate with the control unit via a protocol. The wearable device has a display screen. The control unit transmits a note content corresponding to the briefing content to the wearable device via the protocol. The wearable device displays the received note content on the display screen of the wearable device.

Abstract: An apparatus of system level simulation and emulation and an associated method are provided, where the apparatus includes: a simulation/emulation engine, an existing intellectual property (IP) installation platform, a speed driver, and an IP proxy. The simulation/emulation engine is utilized for performing at least one of simulation and emulation to make the apparatus be equipped with a first portion of a plurality of IP modules. The existing IP installation platform is utilized for installing a chip equipped with existing IP modules to make the apparatus be equipped with a second portion of the plurality of IP modules, where the second portion of the plurality of IP modules includes a specific IP module of the existing IP modules. With the aid of the speed driver, the apparatus utilizes the specific existing IP module without introducing any unnecessary delay.

Abstract: An exemplary heat dissipating system includes a motherboard, a plurality of temperature sensors connected to the motherboard for sampling a temperature of the motherboard, a FCB establishing a wireless communication with the motherboard, and a plurality of fans. The motherboard receives and processes the temperature data from the plurality of temperature sensors to transform the temperature data into a wireless signal. The FCB obtains the temperature data through the wireless communication, and controls the rotation speed of the plurality of fans according to the temperature data.

Abstract: A fan control system for controlling the rotation speed of a number of fans includes one or more first motherboards with baseboard management controllers (BMCs), one or more second motherboards without any BMCs, one or more temperature sensors for detecting the temperature in the area of the second motherboards, and a fan control board (FCB). Based on determining whether there are any BMCs mounted in the motherboards or not, the FCB reads motherboard temperature from the BMCs mounted in the first motherboards, or reads the temperature from the temperature sensors, thereby controlling the corresponding fans.

Abstract: A fan control system for controlling the rotation speed of a number of fans includes motherboards corresponding to the fans, a network switch connected to the motherboards, a dynamic host configuration protocol (DHCP) server connected to the network switch, and a fan control board (FCB). The FCB gets port IDs and Internet Protocol (IP) addresses corresponding to the motherboards by reading a Media Access Control (MAC) address table from the network switch and an IP address table from the DHCP server, thereby reading the motherboard temperature from BMCs mounted on the motherboards to control the rotation speed of the fans.

Abstract: A system-level emulation/verification system includes an operating device for using a simulator to set soft intellectual properties (soft IPs) corresponding to a System-on-Chip (SOC) design module, executing a simulation corresponding to the SOC design module, and using a transactor to interact with the simulator via an Application Programming Interface (API); and a hard-wired based platform, including a hard IP corresponding to a soft IP of the SOC design module, wherein the hard-wired based platform sets the hard IP according to a setting of the SOC design module, and outputs an operating result of the hard IP corresponding to the setting of the SOC design module. The hard-wired based platform executes an IP model proxy for receiving an output of the transactor, transmitting the output to the hard-wired platform for controlling the operation of the hard IP, and transmitting the operating result to the transactor executed by the operating device.

Abstract: Chip-packaging with bonding options having a plurality of package substrates. The chip-packaging includes first and second package substrates, a chip, and a lead. The chip having a plurality of bonding pads is mounted on the first package substrate. One of these bonding pads is connected to the first package substrate. Another bonding pad is connected to the second package substrate. The lead is connected to one bonding pad. The first and second package substrates have first and second voltages, respectfully. The first voltage and the second voltage are different, and each can be a GND voltage or a POWER voltage. With connection of these bonding pads with the lead or connection of these bonding pads with two package substrates, input ends or output ends in the chip could be connected to a GND voltage or a POWER voltage, or to one pin of the chip-packaging.

Abstract: A method for verifying a branch prediction mechanism and an accessible recording medium for storing a verification program are provided. The method is used for verifying the branch prediction mechanism, such as a branch target buffer (BTB), in a processor. The method comprises providing and executing a verification program in the processor. The verification program comprises at least one branch instruction, which determines whether to use a recursive call and execute the verification program according to a given condition.

Abstract: A de-skew multiplier clock synthesizer with a clock divider outside the feedback loop of a PLL is provided. The clock synthesizer includes a phase locked loop (PLL), a clock divider, and a phase comparator. The PLL receives a reference clock and generates a PLL output clock. The clock divider receives the PLL output clock and generates a first output clock. The phase comparator receives the reference clock, the PLL output clock, and the first output clock and generates a phase difference signal. The clock divider adjusts the first output clock to be in phase with the reference clock according to the phase difference signal.