Patents by Inventor Cheng-Yen Lin

Cheng-Yen Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12242321
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: March 4, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Wen Che Chung, Hui Chuan Lo, Hao-Hsuan Lin, Chun Tsao, Jun-Fu Chen, Ming-Hung Yao, Jia-Wei Zhang, Kuan-Lun Chen, Ting-Chao Lin, Cheng-Yen Lin, Chunyen Lai
  • Publication number: 20240069618
    Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.
    Type: Application
    Filed: April 27, 2023
    Publication date: February 29, 2024
    Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
  • Publication number: 20240008169
    Abstract: An electronic device is provided in this disclosure. The electronic device includes a display panel, a transmission line, a universal motherboard, and an optional panel power management module. The display panel is a first type display panel or a second type display panel. The transmission line is a first transmission line or a second transmission line. The universal motherboard is connected to the first type display panel through the first transmission line, or connected to the second type display panel through the second transmission line. When the display panel is the first type display panel, the panel power management module is connected to the universal motherboard and the first type display panel through the first transmission line, so that the panel power management module provides power management required for the first type display panel according to the universal motherboard.
    Type: Application
    Filed: November 18, 2022
    Publication date: January 4, 2024
    Inventors: Meng-Feng Lin, Tung-Yun Kao, Chao-Kai Wu, Huan-Wen Chen, Cheng-Yen Lin, Jian-Jia Li
  • Patent number: 11551923
    Abstract: A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: January 10, 2023
    Assignee: PHOENIX SILICON INTERNATIONAL CORP.
    Inventors: Chien-Hsiung Huang, Chao-Tsung Tsou, Cheng-Yen Lin
  • Publication number: 20220230869
    Abstract: A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: CHIEN-HSIUNG HUANG, CHAO-TSUNG TSOU, CHENG-YEN LIN
  • Publication number: 20220228250
    Abstract: A crucible includes a crucible body and at least one protrusion. The crucible body has a containing groove. The protrusion is disposed on an outer wall surface of the crucible body. The protrusion protrudes outward from the outer wall of the crucible body. A vapor deposition apparatus includes a metal base and a crucible. The crucible is disposed in the metal base. The crucible includes a crucible body and at least one protrusion. The crucible body has a containing groove, and the containing groove is used for adding a vapor deposition material. The protrusion is disposed on an outer wall surface of the crucible body. The protrusion protrudes outward from the outer wall of the crucible body, and the protrusion abuts the inner wall of the metal base.
    Type: Application
    Filed: January 15, 2021
    Publication date: July 21, 2022
    Inventors: CHIEN-HSIUNG HUANG, CHAO-TSUNG TSOU, CHENG-YEN LIN
  • Patent number: 11348548
    Abstract: A display device includes a first gate line, a second gate line, a first data line and a second data line. The second gate line is disposed adjacent to the first gate line. The first gate line and the second gate line are disposed in parallel and extend in a first direction. The first data line and the second data line are disposed in parallel and extend in a second direction perpendicular to the first direction. There is no thin film transistor disposed adjacent to at least one of the following intersections: the intersection of the first gate line and the first data line; the intersection of the first gate line and the second data line; the intersection of the second gate line and the first data line; and the intersection of the second gate line and the second data line.
    Type: Grant
    Filed: November 5, 2020
    Date of Patent: May 31, 2022
    Assignee: INNOLUX CORPORATION
    Inventor: Cheng-Yen Lin
  • Patent number: 11112845
    Abstract: A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: September 7, 2021
    Assignees: National Taiwan University, MFDIATEK INC.
    Inventors: Wen-Li Shih, Jenq-Kuen Lee, Cheng-Yen Lin, Ming-Yu Hung
  • Publication number: 20210056921
    Abstract: A display device includes a first gate line, a second gate line, a first data line and a second data line. The second gate line is disposed adjacent to the first gate line. The first gate line and the second gate line are disposed in parallel and extend in a first direction. The first data line and the second data line are disposed in parallel and extend in a second direction perpendicular to the first direction. There is no thin film transistor disposed adjacent to at least one of the following intersections: the intersection of the first gate line and the first data line; the intersection of the first gate line and the second data line; the intersection of the second gate line and the first data line; and the intersection of the second gate line and the second data line.
    Type: Application
    Filed: November 5, 2020
    Publication date: February 25, 2021
    Inventor: Cheng-Yen LIN
  • Patent number: 10810705
    Abstract: A video dehazing method includes: capturing a hazy image including multiple inputted pixels by an image capture module, calculating an atmospheric light value according to the inputted pixels by an atmospheric light estimation unit, determining a sky image area according to the inputted pixels via the intermediate calculation results of a guided filter by a sky detection unit; calculating a dark channel image according to the inputted pixels based on dark channel prior (DCP) by a dark channel prior unit; calculating a fine transmission image according to the inputted pixels, the atmospheric light value, the sky image area and the dark channel image via a guided filter by a transmission estimation unit, generating a dehazing image according to the inputted pixels, the atmospheric light value and the fine transmission image by an image dehazing unit, and outputting the dehazing image by a video outputting module.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 20, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Jiun-In Guo, Cheng-Yen Lin
  • Patent number: 10563185
    Abstract: A beta-glucosidase having improved enzymatic activity is disclosed. The amino acid sequence of the beta-glucosidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of tyrosine at position 286 with phenylalanine, or a substitution of asparagine at position 639 with glutamate.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: February 18, 2020
    Assignee: DONGGUAN APAC BIOTECHNOLOGY CO., LTD.
    Inventors: Hui-Lin Lai, Ya-Shan Cheng, Tzu-Hui Wu, Cheng-Yen Lin, Ting-Yung Huang, I-Hsuan Lin, Cheng-Bin Zheng
  • Publication number: 20190287219
    Abstract: A video dehazing method includes: capturing a hazy image including multiple inputted pixels by an image capture module, calculating an atmospheric light value according to the inputted pixels by an atmospheric light estimation unit, determining a sky image area according to the inputted pixels via the intermediate calculation results of a guided filter by a sky detection unit; calculating a dark channel image according to the inputted pixels based on dark channel prior (DCP) by a dark channel prior unit; calculating a fine transmission image according to the inputted pixels, the atmospheric light value, the sky image area and the dark channel image via a guided filter by a transmission estimation unit, generating a dehazing image according to the inputted pixels, the atmospheric light value and the fine transmission image by an image dehazing unit, and outputting the dehazing image by a video outputting module.
    Type: Application
    Filed: June 11, 2018
    Publication date: September 19, 2019
    Inventors: Jiun-In GUO, Cheng-Yen LIN
  • Patent number: 10385346
    Abstract: A xylosidase having improved enzymatic activity is disclosed. The amino acid sequence of the xylosidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of phenylalanine at position 35 with glutamate, and/or a substitution of glutamine at position 41 with histidine.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: August 20, 2019
    Assignee: DONGGUAN APAC BIOTECHNOLOGY CO., LTD.
    Inventors: Ya-Shan Cheng, Tzu-Hui Wu, Cheng-Yen Lin, Hui-Lin Lai, Cheng-Bin Zheng, Ting-Yung Huang, I-Hsuan Lin, Jian-Wen Huang, Chun-Chi Chen, Rey-Ting Guo
  • Publication number: 20190119687
    Abstract: A xylosidase having improved enzymatic activity is disclosed. The amino acid sequence of the xylosidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of phenylalanine at position 35 with glutamate, and/or a substitution of glutamine at position 41 with histidine.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 25, 2019
    Inventors: Ya-Shan Cheng, Tzu-Hui Wu, Cheng-Yen Lin, Hui-Lin Lai, Cheng-Bin Zheng, Ting-Yung Huang, I-Hsuan Lin, Jian-Wen Huang, Chun-Chi Chen, Rey-Ting Guo
  • Patent number: 10233430
    Abstract: A glucose oxidase having improved thermostability is disclosed. The amino acid sequence of the glucose oxidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of glutamate at position 129 with proline, and/or a substitution of glutamine at position 243 with valine.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: March 19, 2019
    Assignee: DONGGUAN APAC BIOTECHNOLOGY CO.,LTD.
    Inventors: Ya-Shan Cheng, Tzu-Hui Wu, Cheng-Yen Lin, Hui-Lin Lai, Cheng-Bin Zheng, Ting-Yung Huang, I-Hsuan Lin, Jian-Wen Huang, Chun-Chi Chen, Rey-Ting Guo
  • Patent number: 10217415
    Abstract: A display device includes a plurality of sub-pixels. The display device displays a specific image composed of display lines. A display line of the specific image is supplied to a portion of the sub-pixels through the data lines to form an arrangement of brightness and darkness with a period of Q×M, and a pixel is composed by Q sub-pixels. The plurality of sub-pixels corresponding to the display line have a polarity distribution with a second period of 2N, and 2N sub-pixels in one period are divided into a first region containing first to N-th sub-pixels and a second region containing (N+1)-th to 2N-th sub-pixels. The polarity distribution of the first to N-th sub-pixels is opposite to that of the (N+1)-th to 2N-th sub-pixels. The least common multiple of M and N is an odd multiple of N.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: February 26, 2019
    Assignee: INNOLUX CORPORATION
    Inventor: Cheng-Yen Lin
  • Publication number: 20180336854
    Abstract: A display panel includes a first gate line, a second gate line, a first data line and a second data line. The first pixel unit and the second pixel unit are disposed between the first gate line and the second gate line. During a first period of time, a first scan pulse is provided to the first gate line, a voltage on the first data line is changed from a first predefined voltage to a first voltage, thereby generating a first voltage shift, and a voltage on the second data line is changed from a second predefined voltage to a second voltage, thereby generating a second voltage shift. One of the first voltage shift and the second voltage shift is greater than zero, and the other is less than zero.
    Type: Application
    Filed: May 9, 2018
    Publication date: November 22, 2018
    Inventor: Cheng-Yen LIN
  • Patent number: 10026603
    Abstract: A manufacturing process of wafer thinning includes a step of wafer-grinding to grind a surface of a wafer to a first predetermined thickness, and a step of wafer-etching to etch the grinded face of the wafer with the first predetermined thickness to a second predetermined thickness.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 17, 2018
    Assignee: PHOENIX SILICON INTERNATIONAL CORP.
    Inventors: Shih-Ching Yang, Chien-Hsiung Huang, Chao-Tsung Tsou, Cheng-Yen Lin
  • Patent number: 10011822
    Abstract: A phytase having improved thermostability is disclosed. The phytase has a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is one of mutations A to D. The mutation A is to substitute amino acids at positions 143 and 262 with cysteine, the mutation B is to substitute amino acids at positions 259 and 312 with cysteine, the mutation C is to substitute amino acids at positions 205 and 257 with cysteine, and the mutation D is to substitute amino acids at positions 264 and 309 with cysteine.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: July 3, 2018
    Assignee: DONGGUAN APAC BIOTECHNOLOGY CO., LTD.
    Inventors: Tzu-Hui Wu, Ya-Shan Cheng, Hui-Lin Lai, Cheng-Yen Lin, Tsung-Yu Ko, Jian-Wen Huang, Chun-Chi Chen, Rey-Ting Guo
  • Patent number: 9944915
    Abstract: A cellulase having improved thermostability is disclosed. The cellulase comprises a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is adding a cysteine in N terminal and adding a glycine and a cysteine or adding a proline and a cysteine in C terminal.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: April 17, 2018
    Assignee: DONGGUAN APAC BIOTECHNOLOGY CO., LTD.
    Inventors: Rey-Ting Guo, Ya-Shan Cheng, Jian-Wen Huang, Tzu-Hui Wu, Hui-Lin Lai, Cheng-Yen Lin, Tsung-Yu Ko