Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.

Abstract: A package structure includes a first RDL, an adhesive layer and a first electronic component. Upper bumps and conductive pads are provided on a first upper surface and a first lower surface of the first RDL, respectively. The adhesive layer is located on the first upper surface of the first RDL and surrounds the upper bumps. The first electronic component is mounted on the adhesive layer and includes conductors which are visible from an active surface of the first electronic component and joined to the upper bumps, the active surface of the first electronic component faces toward the first upper surface of the first RDL. Two adhesive surfaces of the adhesive layer are adhered to the first upper surface of the first RDL and the active surface of the first electronic component, respectively.

Abstract: A semiconductor structure includes a functional die, a dummy die, a redistribution structure, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The redistribution structure is disposed over and electrically connected to the functional die. The seal ring is disposed over the dummy die. The alignment mark is between the seal ring and the redistribution structure, wherein the alignment mark is electrically isolated from the dummy die, the redistribution structure and the seal ring. The insulating layer encapsulates the functional die and the dummy die.

Abstract: A method for removing a heavy metal from water includes subjecting a microbial solution containing a liquid culture of a urease-producing bacterial strain and a reaction solution containing a manganese compound and urea to a microbial-induced precipitation reaction, so as to obtain biomineralized manganese carbonate (MnCO3) particles, admixing the biomineralized MnCO3 particles with water containing a heavy metal, so that the biomineralized MnCO3 particles adsorb the heavy metal in the water to form a precipitate, and removing the precipitate from the water.

Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.

Abstract: An electronic device is provided in this disclosure. The electronic device includes a display panel, a transmission line, a universal motherboard, and an optional panel power management module. The display panel is a first type display panel or a second type display panel. The transmission line is a first transmission line or a second transmission line. The universal motherboard is connected to the first type display panel through the first transmission line, or connected to the second type display panel through the second transmission line. When the display panel is the first type display panel, the panel power management module is connected to the universal motherboard and the first type display panel through the first transmission line, so that the panel power management module provides power management required for the first type display panel according to the universal motherboard.

Abstract: A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.

Abstract: A crucible includes a crucible body and at least one protrusion. The crucible body has a containing groove. The protrusion is disposed on an outer wall surface of the crucible body. The protrusion protrudes outward from the outer wall of the crucible body. A vapor deposition apparatus includes a metal base and a crucible. The crucible is disposed in the metal base. The crucible includes a crucible body and at least one protrusion. The crucible body has a containing groove, and the containing groove is used for adding a vapor deposition material. The protrusion is disposed on an outer wall surface of the crucible body. The protrusion protrudes outward from the outer wall of the crucible body, and the protrusion abuts the inner wall of the metal base.

Abstract: A Taiko wafer ring cut process method is provided. The Taiko wafer ring cut process method includes the following steps. A Taiko wafer is disposed on the platform. The Taiko wafer is performing by laser ring cutting so that a Taiko ring and an edge portion of the Taiko wafer are separated from a wafer portion of the Taiko wafer. The wafer portion of the Taiko wafer is adhered to a frame.

Abstract: A display device includes a first gate line, a second gate line, a first data line and a second data line. The second gate line is disposed adjacent to the first gate line. The first gate line and the second gate line are disposed in parallel and extend in a first direction. The first data line and the second data line are disposed in parallel and extend in a second direction perpendicular to the first direction. There is no thin film transistor disposed adjacent to at least one of the following intersections: the intersection of the first gate line and the first data line; the intersection of the first gate line and the second data line; the intersection of the second gate line and the first data line; and the intersection of the second gate line and the second data line.

Abstract: A probabilistic framework for compiler optimization with multithread power-gating controls includes scheduling all thread fragments of a multithread computer code with the estimated execution time, logging all time stamps of events, and sorting and unifying the logged time stamps. Time slices are constructed using adjacent time stamps of each thread fragment. A power-gating time having a component turned off for each time slice is determined. Power-gateable windows that reduce energy consumption of the time slice is determined according to the power-gating time. The compiler inserts predicated power-gating instructions at locations corresponding to the selected power-gateable windows into the power-gateable computer code.

Abstract: A display device includes a first gate line, a second gate line, a first data line and a second data line. The second gate line is disposed adjacent to the first gate line. The first gate line and the second gate line are disposed in parallel and extend in a first direction. The first data line and the second data line are disposed in parallel and extend in a second direction perpendicular to the first direction. There is no thin film transistor disposed adjacent to at least one of the following intersections: the intersection of the first gate line and the first data line; the intersection of the first gate line and the second data line; the intersection of the second gate line and the first data line; and the intersection of the second gate line and the second data line.

Abstract: A video dehazing method includes: capturing a hazy image including multiple inputted pixels by an image capture module, calculating an atmospheric light value according to the inputted pixels by an atmospheric light estimation unit, determining a sky image area according to the inputted pixels via the intermediate calculation results of a guided filter by a sky detection unit; calculating a dark channel image according to the inputted pixels based on dark channel prior (DCP) by a dark channel prior unit; calculating a fine transmission image according to the inputted pixels, the atmospheric light value, the sky image area and the dark channel image via a guided filter by a transmission estimation unit, generating a dehazing image according to the inputted pixels, the atmospheric light value and the fine transmission image by an image dehazing unit, and outputting the dehazing image by a video outputting module.

Abstract: A beta-glucosidase having improved enzymatic activity is disclosed. The amino acid sequence of the beta-glucosidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of tyrosine at position 286 with phenylalanine, or a substitution of asparagine at position 639 with glutamate.

Abstract: A video dehazing method includes: capturing a hazy image including multiple inputted pixels by an image capture module, calculating an atmospheric light value according to the inputted pixels by an atmospheric light estimation unit, determining a sky image area according to the inputted pixels via the intermediate calculation results of a guided filter by a sky detection unit; calculating a dark channel image according to the inputted pixels based on dark channel prior (DCP) by a dark channel prior unit; calculating a fine transmission image according to the inputted pixels, the atmospheric light value, the sky image area and the dark channel image via a guided filter by a transmission estimation unit, generating a dehazing image according to the inputted pixels, the atmospheric light value and the fine transmission image by an image dehazing unit, and outputting the dehazing image by a video outputting module.

Abstract: A xylosidase having improved enzymatic activity is disclosed. The amino acid sequence of the xylosidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of phenylalanine at position 35 with glutamate, and/or a substitution of glutamine at position 41 with histidine.

Abstract: A xylosidase having improved enzymatic activity is disclosed. The amino acid sequence of the xylosidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of phenylalanine at position 35 with glutamate, and/or a substitution of glutamine at position 41 with histidine.

Abstract: A glucose oxidase having improved thermostability is disclosed. The amino acid sequence of the glucose oxidase is a modified amino acid sequence of SEQ ID NO: 2, wherein the modification is a substitution of glutamate at position 129 with proline, and/or a substitution of glutamine at position 243 with valine.

Abstract: A display device includes a plurality of sub-pixels. The display device displays a specific image composed of display lines. A display line of the specific image is supplied to a portion of the sub-pixels through the data lines to form an arrangement of brightness and darkness with a period of Q×M, and a pixel is composed by Q sub-pixels. The plurality of sub-pixels corresponding to the display line have a polarity distribution with a second period of 2N, and 2N sub-pixels in one period are divided into a first region containing first to N-th sub-pixels and a second region containing (N+1)-th to 2N-th sub-pixels. The polarity distribution of the first to N-th sub-pixels is opposite to that of the (N+1)-th to 2N-th sub-pixels. The least common multiple of M and N is an odd multiple of N.

Abstract: A display panel includes a first gate line, a second gate line, a first data line and a second data line. The first pixel unit and the second pixel unit are disposed between the first gate line and the second gate line. During a first period of time, a first scan pulse is provided to the first gate line, a voltage on the first data line is changed from a first predefined voltage to a first voltage, thereby generating a first voltage shift, and a voltage on the second data line is changed from a second predefined voltage to a second voltage, thereby generating a second voltage shift. One of the first voltage shift and the second voltage shift is greater than zero, and the other is less than zero.