Patents by Inventor Cheng-Yen Wen

Cheng-Yen Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250234610
    Abstract: Methods of forming a low-resistance source/drain feature for a multi-gate device are provided. A example method includes forming a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, forming a bottom dielectric layer over the substrate, depositing a first epitaxial layer over the inner spacers and the sidewalls of the plurality of the channel layers, performing a thermal treatment to reshape the first epitaxial layer, after the performing of the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer. The first epitaxial layer includes germanium and the second epitaxial layer is free of germanium.
    Type: Application
    Filed: May 6, 2024
    Publication date: July 17, 2025
    Inventors: Wei-Min Liu, Cheng-Yen Wen, Ming-Hua Yu, Chii-Horng Li
  • Publication number: 20250234611
    Abstract: The present disclosure describes a semiconductor device having a source/drain (S/D) structure with a void. The semiconductor device includes a stack of semiconductor layers on a substrate, a gate structure surrounding the stack of semiconductor layers, and a S/D structure on the substrate and in contact with the stack of semiconductor layers. The S/D structure includes a void below a top surface of the S/D structure.
    Type: Application
    Filed: July 3, 2024
    Publication date: July 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei KWOK, Wei Hao LU, Cheng-Yen WEN, Ming-Hua YU, Chii-Horng LI
  • Patent number: 12363945
    Abstract: A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: July 15, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsz-Mei Kwok, Yung-Chun Yang, Cheng-Yen Wen, Li-Li Su, Yee-Chia Yeo
  • Publication number: 20250203904
    Abstract: The present disclosure is directed to a structure of a gate-all-around field effect transistors (GAAFET) and a method of forming the structure. The structure includes a diffusion barrier structure in an S/D epitaxial structure of the GAAFET. The diffusion barrier structure is in contact with an NS layer of the GAAFET and extends over side surfaces of inner spacer structures adjacent to the NS layer. The diffusion barrier structure separates a high doping region of the S/D epitaxial structure from the NS layer and regions of the inner spacer structures close to the NS layer. The diffusion barrier structure prevents (or mitigates) dopants in the high doping region from diffusing into the NS layer and the inner spacer structures, preserving the integrity of the NS layer as a semiconducting channel of the GAAFET and avoiding a current crowding effect.
    Type: Application
    Filed: January 5, 2024
    Publication date: June 19, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei Hao LU, Cheng-Yen WEN, Chii-Horng LI
  • Publication number: 20230369502
    Abstract: A semiconductor device including a seeding layer in the source/drain region and a method of forming is provided. The semiconductor device may include a plurality of nanostructures over a substrate, a gate wrapping around the plurality of nanostructures, a source/drain region adjacent the plurality of nanostructures, and inner spacers between the source/drain region and the gate stack. The source/drain region may include a polycrystalline seeding layer covering sidewalls of the plurality of nanostructures and sidewalls of the inner spacers, and a semiconductor layer over the seeding layer. The semiconductor layer may have a higher dopant concentration than the seeding layer.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Shao-Yang Ma, Cheng-Yen Wen, Li-Li Su, Chil-Horng Li, Yee-Chia Yeo
  • Publication number: 20230343819
    Abstract: Provided is an epitaxial structure and a method for forming such a structure. The method includes forming a fin structure on a substrate, wherein the fin structure includes a semiconductor material having substantially a {110} crystallographic orientation. The method includes etching a portion of the fin structure to expose a sidewall portion of the semiconductor material. Further, the method includes growing an epitaxial structure on the sidewall of the semiconductor material, wherein the epitaxial structure propagates with facets having a {110} crystallographic orientation.
    Type: Application
    Filed: April 26, 2022
    Publication date: October 26, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Min Liu, Tsz-Mei Kwok, Yung-Chun Yang, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo, Hui-Lin Huang
  • Publication number: 20230275123
    Abstract: In an embodiment, a device includes: a semiconductor fin extending from a semiconductor substrate; a nanostructure above the semiconductor fin; a source/drain region adjacent a channel region of the nanostructure; a bottom spacer between the source/drain region and the semiconductor fin; and a gap between the bottom spacer and the source/drain region.
    Type: Application
    Filed: June 8, 2022
    Publication date: August 31, 2023
    Inventors: Wei-Min Liu, Tsz-Mei Kwok, Hui-Lin Huang, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20230187524
    Abstract: A method includes forming a stack of layers, which includes a plurality of semiconductor nano structures and a plurality of sacrificial layers. The plurality of semiconductor nano structures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, forming inner spacers in the lateral recesses, and epitaxially growing a source/drain region from the plurality of semiconductor nano structures. The source/drain region is spaced apart from the inner spacers by air inner spacers.
    Type: Application
    Filed: May 11, 2022
    Publication date: June 15, 2023
    Inventors: Wei-Min Liu, Cheng-Yen Wen, Li-Li Su, Chii-Horng Li, Yee-Chia Yeo
  • Publication number: 20230028591
    Abstract: A method includes forming a protruding semiconductor stack including a plurality of sacrificial layers and a plurality of nanostructures, with the plurality of sacrificial layers and the plurality of nanostructures being laid out alternatingly. The method further includes forming a dummy gate structure on the protruding semiconductor stack, etching the protruding semiconductor stack to form a source/drain recess, and forming a source/drain region in the source/drain recess. The formation of the source/drain region includes growing first epitaxial layers. The first epitaxial layers are grown on sidewalls of the plurality of nanostructures, and a cross-section of each of the first epitaxial layers has a quadrilateral shape. The first epitaxial layers have a first dopant concentration. The formation of the source/drain region further includes growing a second epitaxial layer on the first epitaxial layers. The second epitaxial layer has a second dopant concentration higher than the first dopant concentration.
    Type: Application
    Filed: April 4, 2022
    Publication date: January 26, 2023
    Inventors: Tsz-Mei Kwok, Yung-Chun Yang, Cheng-Yen Wen, Li-Li Su, Yee-Chia Yeo
  • Patent number: 8442438
    Abstract: A wireless transmitter includes a first filtering unit coupled to a first cable for outputting a first DC source transmitted on the first cable, a first power converting unit for converting the first DC source into a second DC source, a second filtering unit for eliminating noise in the second DC source, a first DC blocking unit for blocking the second DC source and outputting a second frequency modulation (FM) signal, an amplifier for amplifying the second FM signal to generate a first FM signal, and a second DC blocking unit coupled to the amplifier and the first cable, for outputting the first FM signal to the first cable, such that the first FM signal is transmitted to the air through the first cable as a transmitting antenna.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 14, 2013
    Assignee: Wistron NeWeb Corporation
    Inventors: Cheng-Hsiung Hsu, Chung-Wei Hsu, Cheng-Yen Wen, Chun-Chia Kuo
  • Publication number: 20110026634
    Abstract: A wireless transmitter includes a first filtering unit coupled to a first cable for outputting a first DC source transmitted on the first cable, a first power converting unit for converting the first DC source into a second DC source, a second filtering unit for eliminating noise in the second DC source, a first DC blocking unit for blocking the second DC source and outputting a second frequency modulation (FM) signal, an amplifier for amplifying the second FM signal to generate a first FM signal, and a second DC blocking unit coupled to the amplifier and the first cable, for outputting the first FM signal to the first cable, such that the first FM signal is transmitted to the air through the first cable as a transmitting antenna.
    Type: Application
    Filed: June 30, 2010
    Publication date: February 3, 2011
    Inventors: Cheng-Hsiung Hsu, Chung-Wei Hsu, Cheng-Yen Wen, Chun-Chia Kuo