Patents by Inventor Cheng-Yen YU
Cheng-Yen YU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947208Abstract: This invention discloses a display panel including a first substrate, light emitting elements, a touch sensing structure and a conductive layer. The light emitting elements are disposed on the first substrate. The touch sensing structure is disposed on the first substrate and on a side away from a light emitting surface of the light emitting elements. The conductive layer is disposed between the light emitting elements and the first substrate and includes contacts or at least a portion of the touch sensing structure, and the light emitting elements and the contacts are electrically connected.Type: GrantFiled: August 15, 2022Date of Patent: April 2, 2024Assignee: HANNSTAR DISPLAY CORPORATIONInventors: Jing-Xuan Chen, Cheng-Yen Yeh, Mu-Kai Kang, Sz-Kai Huang, Ming-Chang Yu
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Publication number: 20240088297Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen YU, Po-Chi WU, Yueh-Chun LAI
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Publication number: 20240072667Abstract: A switching regulator includes a boost power stage circuit and a control circuit. The boost power stage circuit includes: at least one power switch configured to switch a terminal of an inductor according to an operation signal during a normal operation period, such that the terminal of the inductor is switched between an output voltage and ground level; and a power line switch connected in series to the inductor between the input voltage and the output voltage. The power line switch is turned OFF when the output voltage is short to ground level, to prevent a short current from flowing from input voltage to ground level. The control circuit generates the operation signal according to the output voltage and determines whether the power line switch is P-type or N-type MOS device, so as to turn OFF the power line switch when the output voltage is short to ground level.Type: ApplicationFiled: July 25, 2023Publication date: February 29, 2024Inventors: Pao-Hsun Yu, Shei-Chie Yang, Yuan-Yen Mai, Cheng-Hung Hsu
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Patent number: 11855222Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.Type: GrantFiled: July 1, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yen Yu, Po-Chi Wu, Yueh-Chun Lai
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Patent number: 11705519Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: GrantFiled: June 21, 2021Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
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Publication number: 20220336667Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Cheng-Yen YU, Po-Chi WU, Yueh-Chun LAI
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Patent number: 11387365Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.Type: GrantFiled: April 1, 2020Date of Patent: July 12, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Yu, Po-Chi Wu, Yueh-Chun Lai
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Publication number: 20210313469Abstract: In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, a plasma process combining etching and deposition processes is used to form a recess having a rounded corner shape in a cross section along the second direction.Type: ApplicationFiled: April 1, 2020Publication date: October 7, 2021Inventors: Cheng-Yen YU, Po-Chi WU, Yueh-Chun LAI
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Publication number: 20210313468Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: ApplicationFiled: June 21, 2021Publication date: October 7, 2021Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
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Patent number: 11043593Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: GrantFiled: October 7, 2019Date of Patent: June 22, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
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Publication number: 20200035832Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: ApplicationFiled: October 7, 2019Publication date: January 30, 2020Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
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Patent number: 10483394Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: GrantFiled: August 6, 2018Date of Patent: November 19, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
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Publication number: 20180342619Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: ApplicationFiled: August 6, 2018Publication date: November 29, 2018Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
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Patent number: 10043906Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: GrantFiled: January 10, 2017Date of Patent: August 7, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
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Patent number: 9991385Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.Type: GrantFiled: September 15, 2015Date of Patent: June 5, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tung-Wen Cheng, Che-Cheng Chang, Mu-Tsang Lin, Bo-Feng Young, Cheng-Yen Yu
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Publication number: 20170133506Abstract: A semiconductor device includes a Fin FET device. The Fin FET device includes a first fin structure extending in a first direction and protruding from an isolation insulating layer, a first gate stack including a first gate electrode layer and a first gate dielectric layer, covering a portion of the first fin structure and extending in a second direction perpendicular to the first direction, and a first source and a first drain, each including a first stressor layer disposed over the first fin structure. The first fin structure and the isolation insulating layer are disposed over a substrate. A height Ha of an interface between the first fin structure and the first stressor layer measured from the substrate is greater than a height Hb of a lowest height of the isolation insulating layer measured from the substrate.Type: ApplicationFiled: January 10, 2017Publication date: May 11, 2017Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao ZHANG, Bo-Feng YOUNG
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Publication number: 20170077302Abstract: The present disclosure relates to a semiconductor device that controls a strain on a channel region by forming a dielectric material in recesses, adjacent to a channel region, in order to provide control over a volume and shape of a strain inducing material of epitaxial source/drain regions formed within the recesses. In some embodiments, the semiconductor device has epitaxial source/drain regions arranged in recesses within an upper surface of a semiconductor body on opposing sides of a channel region. A gate structure is arranged over the channel region, and a dielectric material is arranged laterally between the epitaxial source/drain regions and the channel region. The dielectric material consumes some volume of the recesses, thereby reducing a volume of strain inducing material in epitaxial source/drain regions formed in the recesses.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Tung-Wen Cheng, Che-Cheng Chang, Mu-Tsang Lin, Bo-Feng Young, Cheng-Yen Yu
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Patent number: 9564528Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0?D1?D2 (but D1 and D2 are not zero at the same time).Type: GrantFiled: June 24, 2015Date of Patent: February 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yen Yu, Che-Cheng Chang, Tung-Wen Cheng, Zhe-Hao Zhang, Bo-Feng Young
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Publication number: 20160211372Abstract: A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. An isolation insulating layer is formed so that an upper part of the fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the fin structure. Recesses are formed in the isolation insulating layer at both sides of the fin structure. A recess is formed in a portion of the fin structure which is not covered by the gate structure. The recess in the fin structure and the recesses in the isolation insulating layer are formed such that a depth D1 of the recess in the fin structure and a depth D2 of the recesses in the isolation insulating layer measured from an uppermost surface of the isolation insulating layer satisfy 0?D1?D2 (but D1 and D2 are not zero at the same time).Type: ApplicationFiled: June 24, 2015Publication date: July 21, 2016Inventors: Cheng-Yen YU, Che-Cheng CHANG, Tung-Wen CHENG, Zhe-Hao Zhang, Bo-Feng YOUNG