Patents by Inventor Cheng-Yi Hong
Cheng-Yi Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11855066Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: GrantFiled: May 13, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Patent number: 11508710Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.Type: GrantFiled: May 27, 2020Date of Patent: November 22, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Publication number: 20220271024Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: ApplicationFiled: May 13, 2022Publication date: August 25, 2022Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Patent number: 11335672Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: GrantFiled: July 23, 2020Date of Patent: May 17, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Publication number: 20200357785Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: ApplicationFiled: July 23, 2020Publication date: November 12, 2020Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Publication number: 20200286878Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.Type: ApplicationFiled: May 27, 2020Publication date: September 10, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Patent number: 10741537Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.Type: GrantFiled: October 5, 2017Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COOMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Patent number: 10714463Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.Type: GrantFiled: November 24, 2019Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Publication number: 20200098739Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.Type: ApplicationFiled: November 24, 2019Publication date: March 26, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Patent number: 10504880Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.Type: GrantFiled: April 29, 2019Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Publication number: 20190252363Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.Type: ApplicationFiled: April 29, 2019Publication date: August 15, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Patent number: 10276551Abstract: A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.Type: GrantFiled: December 27, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Publication number: 20190006341Abstract: A semiconductor device package includes a redistribution structure, a first semiconductor device, a plurality of second semiconductor devices, at least one warpage adjusting component, and an encapsulating material. The first semiconductor device is disposed on the redistribution structure. The second semiconductor devices are disposed on the redistribution structure and surround the first semiconductor device. The at least one warpage adjusting component is disposed on at least one of the second semiconductor devices. The encapsulating material encapsulates the first semiconductor device, the second semiconductor devices and the warpage adjusting component, wherein a Young's modulus of the warpage adjusting component is greater than or equal to a Young's modulus of the encapsulating material, and a coefficient of thermal expansion (CTE) of the warpage adjusting component is smaller than a CTE of the encapsulating material.Type: ApplicationFiled: December 27, 2017Publication date: January 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
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Publication number: 20180204828Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.Type: ApplicationFiled: October 5, 2017Publication date: July 19, 2018Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Patent number: 9502323Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.Type: GrantFiled: January 12, 2015Date of Patent: November 22, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yi Lin, Kuo-Chuan Liu, Po-Yao Lin, Cheng-Yi Hong, Ming-Chih Yew
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Publication number: 20150123257Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.Type: ApplicationFiled: January 12, 2015Publication date: May 7, 2015Inventors: Wen-Yi Lin, Kuo-Chuan Liu, Po-Yao Lin, Cheng-Yi Hong, Ming-Chih Yew
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Patent number: 8941248Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.Type: GrantFiled: March 13, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Yi Lin, Ming-Chih Yew, Cheng-Yi Hong, Po-Yao Lin, Kuo-Chuan Liu
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Publication number: 20140264813Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Inventors: Wen-Yi Lin, Ming-Chih Yew, Cheng-Yi Hong, Po-Yao Lin, Kuo-Chuan Liu