Abstract: An edge emitting laser (EEL) device includes a substrate, an n-type buffer layer, a first n-type cladding layer, a grating layer, a spacer layer, a lower confinement unit, an active layer, an upper confinement unit, a p-type cladding layer, a tunnel junction layer and a second n-type cladding layer sequentially arranged from bottom to top. The tunnel junction layer can stop an etching process from continuing to form the second n-type cladding layer into a predetermined ridge structure and converting a part of the p-type cladding layer into the n-type cladding layer to reduce series resistance of the EEL device. Therefore, the optical field and active layer tend to be coupled at the middle of the active layer, the lower half of the active layer can be utilized effectively, and the optical field is near to the grating layer to achieve better optical field/grating coupling efficiency and lower threshold current.

Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a substrate, a first mirror layer, a tunnel junction layer, a second mirror layer, an active layer, an oxide layer and a third mirror layer sequentially stacked with one another. The first mirror layer and the third mirror layer are N-type distributed Bragg reflectors (N-DBR), and the second mirror layer is P-type distributed Bragg reflector (P-DBR). The tunnel junction layer is provided for the VCSEL device to convert a part of the P-DBR into N-DBR to reduce the series resistance of the VCSEL device, and the tunnel junction layer is not used as current-limiting apertures. This disclosure further discloses a VCSEL device manufacturing method with the in-situ and one-time epitaxy features to avoid the risk of process variation caused by moving the device into and out from an epitaxial cavity.

Abstract: A light emitting element includes a substrate, a lower cladding layer, a lower confinement layer, an active layer, an upper confinement layer, an upper cladding layer, a tunnel junction layer, a window layer and an upper electrode sequentially arranged from bottom to top. The tunnel junction layer is for converting the window layer and upper electrode from the p-type of a traditional LED to the n-type of the light emitting element of this disclosure. Since the n-type window layer has a resistance much smaller than that of the p-type window layer, the window layer of this disclosure has low resistance and good current spreading effect to improve the light emitting efficiency. Since the n-type upper electrode has a resistance much lower than that of the p-type upper electrode, the n-type upper electrode of this disclosure is more conducive to ohmic contact than the p-type upper electrode of the traditional LED.

Abstract: An edge emitting laser (EEL) device includes a substrate, an n-type buffer layer, a first n-type cladding layer, a grating layer, a spacer layer, a lower confinement unit, an active layer, an upper confinement unit, a p-type cladding layer, a tunnel junction layer and a second n-type cladding layer sequentially arranged from bottom to top. The tunnel junction layer can stop an etching process from continuing to form the second n-type cladding layer into a predetermined ridge structure and converting a part of the p-type cladding layer into the n-type cladding layer to reduce series resistance of the EEL device. Therefore, the optical field and active layer tend to be coupled at the middle of the active layer, the lower half of the active layer can be utilized effectively, and the optical field is near to the grating layer to achieve better optical field/grating coupling efficiency and lower threshold current.

Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a substrate, a first mirror layer, an active layer, an oxide layer, a second mirror layer, a tunnel junction layer and a third mirror layer sequentially stacked with one another. The first mirror layer and the third mirror layer are N-type distributed Bragg reflectors (N-DBR), and the second mirror layer is P-type distributed Bragg reflector (P-DBR). The tunnel junction layer is provided for the VCSEL device to convert a part of the P-DBR into N-DBR to reduce the series resistance of the VCSEL device, and the tunnel junction layer is not used as current-limiting apertures. This disclosure further discloses a VCSEL device manufacturing method with the in-situ and one-time epitaxy features to avoid the risk of process variation caused by moving the device into and out from an epitaxial cavity.

Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a substrate, a first mirror layer, a tunnel junction layer, a second mirror layer, an active layer, an oxide layer and a third mirror layer sequentially stacked with one another. The first mirror layer and the third mirror layer are N-type distributed Bragg reflectors (N-DBR), and the second mirror layer is P-type distributed Bragg reflector (P-DBR). The tunnel junction layer is provided for the VCSEL device to convert a part of the P-DBR into N-DBR to reduce the series resistance of the VCSEL device, and the tunnel junction layer is not used as current-limiting apertures. This disclosure further discloses a VCSEL device manufacturing method with the in-situ and one-time epitaxy features to avoid the risk of process variation caused by moving the device into and out from an epitaxial cavity.

Abstract: In one exemplary implementation, an electronic apparatus includes: a reference clock source, for generating a reference clock; a global navigation satellite system (GNSS) receiver for receiving satellites signals and the reference clock, comprising: a monitoring circuit, for monitoring a status of the GNSS receiver to generate a monitoring result; and a compensating circuit, coupled to the reference clock source and the monitoring circuit, for compensating the reference clock according to the monitoring result.

Abstract: A satellite receiver for receiving at least a target satellite signal includes a channel selection filter and a controller. The channel selection filter is provided with a plurality of channel selection settings conforming to characteristics of a plurality of satellite signals corresponding to different satellite systems, wherein each of the channel selection settings is to receive at least one of the satellite signals. The controller controls the channel selection filter to enable a target channel selection setting selected from the channel selection settings to thereby receive at least the target satellite signal.

Abstract: In one exemplary implementation, an electronic apparatus includes: a reference clock source, for generating a reference clock; a global navigation satellite system (GNSS) receiver for receiving satellites signals and the reference clock, comprising: a monitoring circuit, for monitoring a status of the GNSS receiver to generate a monitoring result; and a compensating circuit, coupled to the reference clock source and the monitoring circuit, for compensating the reference clock according to the monitoring result.

Abstract: A satellite receiver for receiving at least a target satellite signal includes a channel selection filter and a controller. The channel selection filter is provided with a plurality of channel selection settings conforming to characteristics of a plurality of satellite signals corresponding to different satellite systems, wherein each of the channel selection settings is to receive at least one of the satellite signals. The controller controls the channel selection filter to enable a target channel selection setting selected from the channel selection settings to thereby receive at least the target satellite signal.

Abstract: In one exemplary implementation, an electronic apparatus has a reference clock source for generating a reference clock, a monitoring circuit for monitoring a non-temperature factor indicative of frequency drift occurrence of the reference clock to thereby generate a monitoring result, and a compensating circuit for compensating the reference clock according to the monitoring result. In another exemplary implementation, an electronic apparatus has a reference clock source for generating a reference clock, a processing logic for performing a designated operation according to the reference clock, a monitoring circuit for monitoring a non-temperature factor indicative of frequency drift occurrence of the reference clock to thereby generate a monitoring result, and a compensating circuit for compensating the designated operation according to the monitoring result.

Abstract: An antenna switching system for switching between a first antenna and a second antenna, where a gain of the first antenna is different from a gain of the second antenna, is disclosed. The antenna switching system includes an antenna switch unit and a switch control device. The antenna switch unit is selectively coupled to the first antenna or the second antenna. The switch control device is coupled to the antenna switch unit and utilized for controlling the antenna switch unit to switch between the first antenna and the second antenna according to at least a predetermined threshold value and an incoming wireless signal received from the antenna switch unit to achieve some purposes such as reducing power consumption and anti-jamming.

Abstract: A circuit structure includes a circuit board, a first circuit component mounted on the circuit board, and a second circuit component mounted on the circuit board. The first circuit board has a first ground plane layout including at least one ground plane, and a second ground plane layout including at least one ground plane, where the first ground plane layout is not electrically connected to the second ground plane layout within the circuit board. The first circuit component is electrically connected to the first ground plane layout, and the second circuit component is electrically connected to the second ground plane layout.