Patents by Inventor Cheng-Yi Peng
Cheng-Yi Peng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113221Abstract: A fin field effect transistor (FinFET) device structure is provided. The FinFET device structure includes a plurality of fin structures above a substrate, an isolation structure over the substrate and between the fin structures, and a gate structure formed over the fin structure. The FinFET device structure includes a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The FinFET device structure also includes a metal silicide layer over the S/D structure, and the metal silicide layer is in contact with the isolation structure.Type: ApplicationFiled: November 28, 2023Publication date: April 4, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Hsiung TSAI, Shahaji B. MORE, Cheng-Yi PENG, Yu-Ming LIN, Kuo-Feng YU, Ziwei FANG
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Patent number: 11942376Abstract: Methods of manufacturing a semiconductor structure are provided. One of the methods includes: receiving a substrate including a first conductive region of a first transistor and a second conductive region of a second transistor, wherein the first transistor and the second transistor have different conductive types; performing an amorphization on the first conductive region and the second conductive region; performing an implantation over the first conductive region of the first transistor; forming a contact material layer over the first conductive region and the second conductive region; performing a thermal anneal on the first conductive region and the second conductive region; and performing a laser anneal on the first conductive region and the second conductive region.Type: GrantFiled: August 8, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun Hsiung Tsai, Cheng-Yi Peng, Ching-Hua Lee, Chung-Cheng Wu, Clement Hsingjen Wann
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Patent number: 11935890Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.Type: GrantFiled: April 11, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
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Publication number: 20240088267Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.Type: ApplicationFiled: November 22, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yi PENG, Chih Chieh YEH, Chih-Sheng CHANG, Hung-Li CHIANG, Hung-Ming CHEN, Yee-Chia YEO
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Patent number: 11929422Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers.Type: GrantFiled: July 29, 2022Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee
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Patent number: 11881530Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions.Type: GrantFiled: January 24, 2022Date of Patent: January 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Song-Bor Lee
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Patent number: 11855208Abstract: A method for forming a FinFET device structure is provided. The method includes forming a fin structure extended above a substrate and forming a gate structure formed over a portion of the fin structure. The method also includes forming a source/drain (S/D) structure over the fin structure, and the S/D structure is adjacent to the gate structure. The method further includes doping an outer portion of the S/D structure to form a doped region, and the doped region includes gallium (Ga). The method includes forming a metal silicide layer over the doped region; and forming an S/D contact structure over the metal silicide layer.Type: GrantFiled: June 11, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsiung Tsai, Shahaji B. More, Cheng-Yi Peng, Yu-Ming Lin, Kuo-Feng Yu, Ziwei Fang
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Patent number: 11855176Abstract: Semiconductor structures are provided. The semiconductor structure includes a fin structure protruding from a substrate and a doped region formed in the fin structure. The semiconductor structure further includes a metal gate structure formed across the fin structure and a gate spacer formed on a sidewall of the metal gate structure. The semiconductor structure further includes a source/drain structure formed over the doped region. In addition, the doped region continuously surrounds the source/drain structure and is in direct contact with the gate spacer.Type: GrantFiled: August 17, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
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Patent number: 11855187Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.Type: GrantFiled: October 11, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Chih Chieh Yeh, Chih-Sheng Chang, Hung-Li Chiang, Hung-Ming Chen, Yee-Chia Yeo
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Publication number: 20230411455Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.Type: ApplicationFiled: August 9, 2023Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Song-Bor Lee
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Publication number: 20230387302Abstract: The structure of a semiconductor device with inner spacer structures between source/drain (S/D) regions and gate-all-around structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate and first and second source/drain (S/D) regions disposed on the substrate. Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions.Type: ApplicationFiled: July 28, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi PENG, Song-Bor LEE
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Patent number: 11824089Abstract: The structure of a semiconductor device with core-shell nanostructured channel regions between source/drain regions of FET devices and a method of fabricating the semiconductor device are disclosed. A semiconductor device includes a substrate, a stack of nanostructured layers with first and second nanostructured regions disposed on the substrate, and nanostructured shell regions wrapped around the second nanostructured regions. The nanostructured shell regions and the second nanostructured regions have semiconductor materials different from each other. The semiconductor device further includes first and second source/drain (S/D) regions disposed on the substrate and a gate-all-around (GAA) structure disposed between the first and second S/D regions, Each of the first and second S/D regions includes an epitaxial region wrapped around each of the first nanostructured regions and the GAA structure is wrapped around each of the nanostructured shell regions.Type: GrantFiled: January 24, 2022Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Song-Bor Lee
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Publication number: 20230369409Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
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Publication number: 20230369451Abstract: A semiconductor structure includes a substrate, a semiconductor fin extending from the substrate, and a silicon germanium (SiGe) epitaxial feature disposed over the semiconductor fin. A gallium-implanted layer is disposed over a top surface of the SiGe epitaxial feature, and a silicide feature is disposed over and in contact with the gallium-implanted layer.Type: ApplicationFiled: July 24, 2023Publication date: November 16, 2023Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
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Patent number: 11798989Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.Type: GrantFiled: June 7, 2022Date of Patent: October 24, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
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Publication number: 20230307522Abstract: A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.Type: ApplicationFiled: April 3, 2023Publication date: September 28, 2023Inventors: Cheng-Yi PENG, Wen-Yuan CHEN, Wen-Hsing HSIEH, Yi-Ju HSU, Jon-Hsu HO, Song-Bor LEE, Bor-Zen TIEN
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Patent number: 11769817Abstract: A semiconductor structure includes a substrate, a semiconductor fin connected to the substrate, an epitaxial layer disposed over the semiconductor fin, and a silicide feature over and in contact with the epitaxial layer. The epitaxial layer including silicon germanium and further includes gallium in an upper portion of the epitaxial layer that is in contact with the silicide feature.Type: GrantFiled: May 11, 2020Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shahaji B. More, Chun Hsiung Tsai, Shih-Chieh Chang, Kuo-Feng Yu, Cheng-Yi Peng
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Patent number: 11749720Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.Type: GrantFiled: December 7, 2020Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
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Patent number: 11728414Abstract: A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, 0.01?x?0.1, and 0.01?y?0.Type: GrantFiled: February 14, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yasutoshi Okuno, Cheng-Yi Peng, Ziwei Fang, I-Ming Chang, Akira Mineji, Yu-Ming Lin, Meng-Hsuan Hsiao
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Patent number: 11695055Abstract: The structure of a semiconductor device with passivation layers on active regions of FET devices and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions disposed on the substrate, nanostructured channel regions disposed between the first and second S/D regions, a passivation layer, and a nanosheet (NS) structure wrapped around the nanostructured channel regions. Each of the S/D regions have a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers. A first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions.Type: GrantFiled: March 3, 2020Date of Patent: July 4, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yi Peng, Ching-Hua Lee, Song-Bor Lee