Abstract: A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The insulating protection layer is disposed on a first active surface of the first chip and includes a concave. Projections of a plurality of first inner pads and a plurality of first outer pads of the first chip projected on the insulating protection layer are located in the concave and out of the concave, respectively. The second chip is flipped on the concave and includes a plurality of second pads. Each of the first inner pads is electrically connected to the corresponding second pad through the corresponding second conductive bump. The underfill is disposed between the concave and the second chip and covers the second conductive bumps.

Abstract: The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.

Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least on opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors.

Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors.

Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.

Abstract: The present stacked semiconductor packages include a bottom package and a top package. The bottom package includes a substrate, a solder mask layer, a plurality of conductive pillars and a die electrically connected to the substrate. The solder mask layer has a plurality of openings exposing a plurality of pads on the substrate. The conductive pillars are disposed on at least a portion of the pads, and protrude from the solder mask layer.

Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.

Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.

Abstract: In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.

Abstract: The present invention relates to a semiconductor package. The semiconductor package includes a substrate, at least one chip, a plurality of conductive elements, a plurality of first conductors and a molding compound. The substrate has a plurality of first pads and a solder mask. The first pads are exposed to a first surface of the substrate, and the material of the first pads is copper. The solder mask is disposed on the first surface, contacts the first pads directly, and has at least one opening so as to expose part of the first pads. The chip is mounted on the first surface of the substrate. The conductive elements electrically connect the chip and the substrate. The first conductors are disposed on the first pads. The molding compound is disposed on the first surface of the substrate, and encapsulates the chip, the conductive elements and part of the first conductors.

Abstract: Described herein are stackable semiconductor device packages and related stacked package assemblies and methods. In one embodiment, a manufacturing method includes: (1) providing a substrate including contact pads disposed adjacent to an upper surface of the substrate; (2) applying an electrically conductive material to form conductive bumps disposed adjacent to respective ones of the contact pads; (3) electrically connecting a semiconductor device to the upper surface of the substrate; (4) applying a molding material to form a molded structure covering the conductive bumps and the semiconductor device; (5) forming a set of cutting slits extending partially through the molded structure and the conductive bumps to form truncated conductive bumps; and (6) reflowing the truncated conductive bumps to form reflowed conductive bumps.

Abstract: A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer.

Abstract: In one embodiment, a manufacturing method includes: (1) applying a first electrically conductive material to an upper surface of a substrate to form first conductive bumps; (2) electrically connecting a semiconductor device to the upper surface of the substrate; (3) applying a molding material to form a molded structure covering the first conductive bumps and the semiconductor device, upper ends of the first conductive bumps being recessed below an upper surface of the molded structure; (4) forming openings adjacent to the upper surface of the molded structure, the openings exposing the upper ends of the first conductive bumps; (5) applying, through the openings, a second electrically conductive material to form second conductive bumps; and (6) forming cutting slits extending through the molded structure and the substrate.

Abstract: In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width WC, and at least one of the openings has a width WU adjacent to an upper surface of the package body, such that WU>WC.

Abstract: A semiconductor package includes: (1) a substrate including an upper surface and a lower surface opposite to the upper surface; (2) a chip mounted and electrically connected to the upper surface of the substrate; (3) an interposer mounted on the chip and electrically connected to the upper surface of the substrate, the interposer including an upper surface and a lower surface that is opposite to the upper surface and facing the chip, the interposer including a plurality of electrical contacts located on the upper surface of the interposer; and (4) a molding compound sealing the substrate, the interposer, and the chip, and exposing the lower surface of the substrate, the molding compound defining a plurality of holes that enclose and expose respective ones of the electrical contacts.

Abstract: A semiconductor package includes a substrate, a chip, an interposer and a molding compound. The chip is electrically connected to the upper surface of the substrate. The interposer is disposed on the chip, and electrically connected to the upper surface of the substrate. The interposer includes an embedded component and a plurality of electric contacts, wherein the embedded component is located between the upper and lower surfaces of the interposer, and the electric contacts are located on the upper surface of the interposer. The molding compound seals the chip and covers the upper surface of the substrate and the lower surface of the interposer.

Abstract: A chip package structure including a first substrate, a chip, a second substrate, a plurality of conductive wires, a plurality of solder balls and a molding compound is provided. The chip is disposed on the first substrate. The second substrate disposed on the chip has an upper surface and a lower surface, in which a distance of the lower surface relative to the chip is smaller than that of the upper surface relative to the chip. The upper surface has a ball mounting surface and a wire bonding surface. A distance between the wire bonding surface and the first substrate is smaller than that between the ball mounting surface and the first substrate. The conductive wires connect the wire bonding surface to the first substrate. The solder balls are disposed on the ball mounting surface. The molding compound is disposed on the first substrate.