Patents by Inventor Cheng Yin

Cheng Yin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12334350
    Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.
    Type: Grant
    Filed: July 10, 2022
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu Lin, Chun-Fu Cheng, Cheng-Yin Wang, Yi-Bo Liao, Szuya Liao
  • Publication number: 20250113596
    Abstract: Embodiments include mixed complementary field effect and unipolar transistors and methods of forming the same. In an embodiment, a structure includes: a first semiconductor nanostructure; a second semiconductor nanostructure; a first isolation structure interposed between the first semiconductor nanostructure and the second semiconductor nanostructure; a first source/drain region extending laterally from an end of the first semiconductor nanostructure, the first source/drain region having a first conductivity type; a second source/drain region extending laterally from an end of the second semiconductor nanostructure, the second source/drain region having the first conductivity type, the second source/drain region aligned vertically with the first source/drain region; and a first gate structure surrounding the first semiconductor nanostructure and the second semiconductor nanostructure.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 3, 2025
    Inventors: Jui-Chien Huang, Cheng-Yin Wang, Wei-Cheng Lin, Kao-Cheng Lin, Szuya Liao
  • Publication number: 20250071964
    Abstract: In an embodiment, a device includes: a first transistor including a first gate structure; a second transistor including a second gate structure, the second gate structure disposed above and coupled to the first gate structure; a third gate structure; a fourth gate structure, the fourth gate structure disposed above and coupled to the third gate structure; a gate isolation region between the first gate structure and the third gate structure, the gate isolation region disposed between the second gate structure and the fourth gate structure; and a cross-coupling contact extending beneath the gate isolation region, the first gate structure, and the third gate structure, the cross-coupling contact coupled to the first gate structure.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Inventors: Tsung-Kai Chiu, Ting-Yun Wu, Cheng-Yin Wang, Szuya Liao
  • Patent number: 12221779
    Abstract: A flushing switch device with automatic pressing stroke detection is provided, which is applied to the flushing switches of a toilet. The flushing switch device with automatic pressing stroke detection includes a capacitive sensor, an actuator, and a protector. The capacitive sensor senses a user's hand movements to generate a sensing signal. The actuator includes a driver and a pressing mechanism; the driver drives the pressing mechanism to press one of the flushing switches. The protector includes a detector and a controller; the detector detects a load variation during an operation of the actuator to generate a detection signal; the controller receives the sensing signal and correspondingly generates a control signal to control the actuator according to the sensing signal and the detection signal.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: February 11, 2025
    Assignee: Taiwan Name Plate Co., Ltd.
    Inventors: Wen-Cheng Yin, Fu-Jung Cheng, Ho-Chuan Hsu, Yu-Hsun Tseng, Chao-Chin Chang, Kai-Li Peng
  • Publication number: 20250006815
    Abstract: A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kao-Cheng LIN, Cheng-Yin WANG, Yen Lin CHUNG, Wei Min CHAN, Yen-Huei CHEN
  • Publication number: 20250006254
    Abstract: A semiconductor device includes a first memory cell and a second memory cell. The first memory cell is configured to store a first data bit at a first node when the first memory cell is turned on. The second memory cell is configured to store the first data bit when the first memory cell is turned off. The first memory cell comprises a first switch coupled to the first node, and the first switch is configured to transmit the first data bit to the second memory cell, and configured to be turned off when the first memory cell is turned off.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Xiang YOU, Cheng-Yin WANG, Szuya LIAO
  • Publication number: 20240381610
    Abstract: The first semiconductor layer and the second semiconductor layer are above the first semiconductor layer, in which the first and second semiconductor layers are vertically spaced apart from each other. The first and second source/drain epitaxial features are respectively on first and second sides of the first semiconductor layer. The third and fourth source/drain epitaxial features are respectively on first and second sides of the second semiconductor layer and above the first source/drain epitaxial feature. The first, third, and fourth source/drain epitaxial features have a first conductive type, and the second source/drain epitaxial feature has a second conductive type opposite to the first conductive type.
    Type: Application
    Filed: May 10, 2023
    Publication date: November 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yin WANG, Wei-Xiang YOU, Kao-Cheng LIN, Jui-Chien HUANG, Szuya LIAO
  • Publication number: 20240336572
    Abstract: The invention relates to substituted indazole propionic acid derivatives, pharmaceutically acceptable salts, tautomers, or pharmaceutically acceptable salts of the tautomers thereof that can activate adenosine 5?-monophosphate-activated protein kinase (AMPK). The invention further relates to pharmaceutical compositions comprising AMPK-activating substituted indazole propionic acid derivatives, pharmaceutically acceptable salts, tautomers, or pharmaceutically acceptable salts of the tautomers thereof and at least one pharmaceutically acceptable excipient, and methods of treating a condition comprising administering AMPK-activating substituted indazole propionic acid derivatives, pharmaceutically acceptable salts, tautomers, or pharmaceutically acceptable salts of the tautomers thereof.
    Type: Application
    Filed: April 4, 2024
    Publication date: October 10, 2024
    Applicant: Pfizer Inc.
    Inventors: Samit Kumar Bhattacharya, Edward Lee Conn, David Christopher Ebner, Brian Stephen Gerstenberger, Chan Woo Huh, Daniel Wei-Shung Kung, Alan Martin Mathiowetz, Jessica Gloria Katherine O'Brien, Meihua Mike Tu, Kimberly O'Keefe Cameron, Dilinie Prasadhini Fernando, Kevin James Filipski, Esther Cheng Yin Lee, Sarah Jane Mear, Aaron Christopher Smith
  • Publication number: 20240314998
    Abstract: A memory structure includes a pull-down transistor and a pull-up transistor stacked vertically in a Z-direction, a pass-gate transistor and a dummy transistor stacked vertically in the Z-direction, a dielectric structure, a connection structure, and a butt contact. The pull-down transistor and the pull-up transistor share a first gate structure. The pass-gate transistor and the dummy transistor share a second gate structure. The dielectric structure is between the first gate structure and the second gate structure in a Y-direction. The connection structure is over and electrically connected to the first gate structure and is over and electrically isolated from the second gate structure. The connection structure is an L-shape in a Y-Z cross-sectional view. The butt contact is directly over the connection structure and the second gate structure. The butt contact is electrically connected to the connection structure and a source/drain feature of the pass-gate transistor.
    Type: Application
    Filed: March 13, 2023
    Publication date: September 19, 2024
    Inventors: Cheng-Yin WANG, Szuya LIAO, Tsung-Kai CHIU, Shao-Tse HUANG, Ting-Yun WU, Wen-Yuan CHEN
  • Publication number: 20240302262
    Abstract: A method and a system for identifying a glacial lake outburst debris flow (GLODF) are provided. The method is obtained based on considering induced influences of slopes of channels and particle sizes of source particles on the GLODF. The method not only compensates for deficiencies in identifying the GLODF, but also realizes determination of the GLODF, which provides data basis for disaster prevention and control layout such as monitoring and early warning on a glacial lake and assists preventing and managing disasters caused by the GLODF. Meanwhile, multiple parameters used in the method are easy and convenient to obtain, and the parameters can be directly used on site, which saves engineering cost, improves working efficiency, and has high practical and promotional value in environmental protection and disaster prevention and mitigation.
    Type: Application
    Filed: March 8, 2024
    Publication date: September 12, 2024
    Inventors: Zhi-quan Yang, Zi-xu Zhang, Wen-qi Jiao, Ying-yan Zhu, Muhammad Asif Khan, Yong-shun Han, Li-ping Liao, Jie Zhang, Wen-fei Xi, Han-hua Xu, Tian-bing Xiang, Xin Zhao, Bi-hua Zhang, Shen-zhang Liu, Cheng-yin Ye
  • Publication number: 20240282364
    Abstract: An SRAM cell includes a first inverter cross-coupled to a second inverter. The first inverter includes a first pull-up transistor and a first pull-down transistor, having coupled drains that define a first storage node. The SRAM cell further includes a first N-type pass-gate transistor having a first drain coupled to a write bit line, a first source coupled to the first storage node, and a first gate coupled to a first write word line. The SRAM cell further includes a first P-type pass-gate transistor having a second drain coupled to the write bit line and a second source coupled to the first storage node. The SRAM cell further includes a P-type transistor having a third drain, coupled to a second gate of the first P-type pass-gate transistor, a third source coupled to a second write word line, and a third gate coupled to an enable signal.
    Type: Application
    Filed: July 26, 2023
    Publication date: August 22, 2024
    Inventors: Wei-Xiang YOU, Szuya LIAO, Cheng-Yin WANG
  • Publication number: 20240257867
    Abstract: Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.
    Type: Application
    Filed: January 31, 2023
    Publication date: August 1, 2024
    Inventors: Wei-Xiang YOU, Wen-Yuan CHEN, Cheng-Yin WANG, Szuya LIAO
  • Publication number: 20240234404
    Abstract: An integrated circuit is provided, including a first cell. The first cell includes a first pair of active regions, at least one first gate, two first conductive segments, and a first interconnect structure. The first pair of active regions extends in a first direction and stacked on each other. The at least one first gate extends in a second direction different from the first direction, and is arranged across the first pair of active regions, to form at least one first pair of devices that are stacked on each other. The first conductive segments are coupled to the first pair of active regions respectively. The first interconnect structure is coupled to at least one of a first via or one of the two first conductive segments.
    Type: Application
    Filed: January 11, 2023
    Publication date: July 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng TZENG, Shih-Wei PENG, Ching-Yu HUANG, Chun-Yen LIN, Wei-Cheng LIN, Jiann-Tyng TZENG, Szuya LIAO, Jui-Chien HUANG, Cheng-Yin WANG, Ting-Yun WU
  • Publication number: 20240140937
    Abstract: Compounds of Formula I that inhibit the activity of the diacylglycerol acyltransferase 2 (DGAT2) and their uses in the treatment of diseases linked thereto in animals are described herein.
    Type: Application
    Filed: November 28, 2023
    Publication date: May 2, 2024
    Applicant: Pfizer Inc.
    Inventors: Markus Boehm, Shawn Cabral, Matthew S. Dowling, Kentaro Futatsugi, Kim Huard, Esther Cheng Yin Lee, Allyn T. Londregan, Jana Polivkova, David A. Price, Qifang Li
  • Patent number: 11958789
    Abstract: A method for determining a consistency coefficient of a power-law cement grout includes: determining a water-cement ratio of the power-law cement grout; according to engineering practice requirements, determining a time required to determine the consistency coefficient of the power-law cement grout; and obtaining the consistency coefficient of the power-law cement grout. The method is accurate and reliable, requires less calculation, etc.; and has very high practical value and popularization value in environmental protection and ecological restoration.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: April 16, 2024
    Assignee: KUNMING UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Zhi-quan Yang, Jun-fan Xiong, Ying-yan Zhu, Yi Yang, Yong-shun Han, Muhammad Asif Khan, Jian-bin Xie, Tian-bing Xiang, Bi-hua Zhang, Han-hua Xu, Jie Zhang, Shen-zhang Liu, Qi-jun Jia, Cheng-yin Ye, Gang Li
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20240014042
    Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.
    Type: Application
    Filed: July 10, 2022
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu Lin, Chun-Fu Cheng, Cheng-Yin Wang, Yi-Bo Liao, Szuya Liao
  • Patent number: 11866425
    Abstract: Compounds of Formula I that inhibit the activity of the diacylglycerol acyltransferase 2 (DGAT2) and their uses in the treatment of diseases linked thereto in animals are described herein.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: January 9, 2024
    Assignee: Pfizer Inc.
    Inventors: Markus Boehm, Shawn Cabral, Matthew S. Dowling, Kentaro Futatsugi, Kim Huard, Esther Cheng Yin Lee, Allyn T. Londregan, Jana Polivkova, David A. Price, Qifang Li
  • Publication number: 20230399833
    Abstract: A flushing switch device with automatic pressing stroke detection is provided, which is applied to the flushing switches of a toilet. The flushing switch device with automatic pressing stroke detection includes a capacitive sensor, an actuator, and a protector. The capacitive sensor senses a user's hand movements to generate a sensing signal. The actuator includes a driver and a pressing mechanism; the driver drives the pressing mechanism to press one of the flushing switches. The protector includes a detector and a controller; the detector detects a load variation during an operation of the actuator to generate a detection signal; the controller receives the sensing signal and correspondingly generates a control signal to control the actuator according to the sensing signal and the detection signal.
    Type: Application
    Filed: March 13, 2023
    Publication date: December 14, 2023
    Inventors: Wen-Cheng Yin, Fu-Jung Cheng, Ho-Chuan Hsu, Yu-Hsun Tseng, Chao-Chin Chang, Kai-Li Peng
  • Publication number: 20230345693
    Abstract: An integrated circuit includes a plurality of SRAM cells. Each SRAM cell includes a first inverter having a first N-type transistor and a first P-type transistor stacked vertically in a first active region. The SRAM cell includes a second inverter cross-coupled with the first inverter and including a second N-type transistor and a second P-type transistor stacked vertically in a second active region. The SRAM cell includes a butt contact electrically connecting an output of the first inverter to an input of the second inverter. The butt contact is at least partially within a first active region.
    Type: Application
    Filed: February 2, 2023
    Publication date: October 26, 2023
    Inventors: Cheng-Yin WANG, Szuya Liao, Jui-Chien Huang