Patents by Inventor CHENG-YING LEE
CHENG-YING LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11959606Abstract: A package structure including a carrier, a photonic device, a supporting frame, and an encapsulant is provided. The photonic device is disposed on the carrier. The supporting frame is disposed on the carrier and surrounds the photonic device. The encapsulant covers the supporting frame and surrounds the photonic device.Type: GrantFiled: March 30, 2021Date of Patent: April 16, 2024Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATIONInventors: Chen-Hsiu Lin, Cheng-Ying Lee, Ming-Sung Tsai
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Publication number: 20240120317Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.Type: ApplicationFiled: July 13, 2023Publication date: April 11, 2024Applicant: Western Digital Technologies, Inc.Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
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Patent number: 11955416Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.Type: GrantFiled: September 15, 2021Date of Patent: April 9, 2024Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Lu, Yun-Yuan Wang, Dai-Ying Lee
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Patent number: 11944019Abstract: A memory device includes a substrate, a transistor disposed over the substrate, an interconnect structure disposed over and electrically connected to the transistor, and a memory stack disposed between two adjacent metallization layers of the interconnect structure. The memory stack includes a bottom electrode disposed over the substrate and electrically connected to a bit line, a memory layer disposed over the bottom electrode, a selector layer disposed over the memory layer, and a top electrode disposed over the selector layer and electrically connected to a word line. Besides, at least one moisture-resistant layer is provided adjacent to and in physical contact with the selector layer, and the at least one moisture-resistant layer includes an amorphous material.Type: GrantFiled: August 27, 2021Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Feng Hsu, Chien-Min Lee, Tung-Ying Lee, Cheng-Hsien Wu, Hengyuan Lee, Xinyu Bao
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Patent number: 11935890Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.Type: GrantFiled: April 11, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
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Publication number: 20240079440Abstract: A multispectral sensing device includes a first die, including silicon, which is patterned to define a first array of sensor elements, which output first electrical signals in response to optical radiation that is incident on the device in a band of wavelengths less than 1000 nm that is incident on the front side of the first die. A second die has its first side bonded to the back side of the first die and includes a photosensitive material and is patterned to define a second array of sensor elements, which output second electrical signals in response to the optical radiation that is incident on the device in a second band of wavelengths greater than 1000 nm that passes through the first die and is incident on the first side of the second die. Readout circuitry reads the first electrical signals and the second electrical signals serially out of the device.Type: ApplicationFiled: September 6, 2022Publication date: March 7, 2024Inventors: Oray O. Cellek, Fei Tan, Gershon Rosenblum, Hong Wei Lee, Cheng-Ying Tsai, Jae Y. Park, Christophe Verove, John L Orlowski, Siddharth Joshi, Xiangli Li, David Coulon, Xiaofeng Fan, Keith Lyon, Nicolas Hotellier, Arnaud Laflaquière
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Patent number: 11787332Abstract: A light-emitting device includes a substrate including circuit pads and a resin portion. A frame disposed on the substrate to form a first space, first to third light sources, and first and second encapsulants. The frame includes an outer wall and a first partition in the first space to form the first space as independent second and third spaces. A first and second light sources are disposed at the second space and provide first and second light beams respectively. A third light source is disposed at the third space and provides a third light beam. A first encapsulant is filled at the second space to seal the first and second light sources. A second encapsulant is filled at the third space to seal the third light source. The second encapsulant includes a first wavelength conversion material converting the third light beam into a fourth light beam.Type: GrantFiled: December 14, 2021Date of Patent: October 17, 2023Assignee: Lite-On Technology CorporationInventors: Kai Yu Hsieh, Chih Chiang Kao, Cheng Ying Lee, Tsung Lin Lu
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Publication number: 20220242305Abstract: A light-emitting device includes a substrate including circuit pads and a resin portion. A frame disposed on the substrate to form a first space, first to third light sources, and first and second encapsulants. The frame includes an outer wall and a first partition in the first space to form the first space as independent second and third spaces. A first and second light sources are disposed at the second space and provide first and second light beams respectively. A third light source is disposed at the third space and provides a third light beam. A first encapsulant is filled at the second space to seal the first and second light sources. A second encapsulant is filled at the third space to seal the third light source. The second encapsulant includes a first wavelength conversion material converting the third light beam into a fourth light beam.Type: ApplicationFiled: December 14, 2021Publication date: August 4, 2022Applicant: Lite-On Technology CorporationInventors: Kai Yu Hsieh, Chih Chiang Kao, Cheng Ying Lee, Tsung Lin Lu
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Publication number: 20210301993Abstract: A package structure including a carrier, a photonic device, a supporting frame, and an encapsulant is provided. The photonic device is disposed on the carrier. The supporting frame is disposed on the carrier and surrounds the photonic device. The encapsulant covers the supporting frame and surrounds the photonic device.Type: ApplicationFiled: March 30, 2021Publication date: September 30, 2021Inventors: CHEN-HSIU LIN, CHENG-YING LEE, MING-SUNG TSAI