Patents by Inventor CHENG-YING LEE

CHENG-YING LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255136
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: March 18, 2025
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Cheng-Hsien Lu, Yun-Yuan Wang, Ming-Hsiu Lee, Dai-Ying Lee
  • Publication number: 20250087600
    Abstract: A semiconductor bonded structure including a first semiconductor chip, at least one second semiconductor chip, a stress adjusting structure, and a circuit layer is provided. The at least one second semiconductor chip is disposed on the first semiconductor chip and electrically connected to the first semiconductor chip. The stress adjusting structure is disposed in at least one of the first semiconductor chip and the at least one second semiconductor chip. The circuit layer is disposed on the at least one second semiconductor chip and the circuit layer is electrically connected to the at least one second semiconductor chip. A fabricating method of the semiconductor bonded structure is also provided. The semiconductor bonded structure may be applied to the fabrication of 3D NAND flash memory with high performance and high capacity.
    Type: Application
    Filed: August 19, 2024
    Publication date: March 13, 2025
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Cheng-Hsien Lu, Ming-Hsiu Lee, Dai-Ying Lee
  • Publication number: 20250076369
    Abstract: A minimum IC operating voltage searching method includes acquiring a corner type of an IC, acquiring ring oscillator data of the IC, generating a first prediction voltage according to the corner type and the ring oscillator data by using a training model, generating a second prediction voltage according to the ring oscillator data by using a non-linear regression approach under an N-ordered polynomial, and generating a predicted minimum IC operating voltage according to the first prediction voltage and the second prediction voltage. N is a positive integer.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 6, 2025
    Applicant: MEDIATEK INC.
    Inventors: Ronald Kuo-Hua Ho, Kun-Yu Wang, Yen-Chang Shih, Sung-Te Chen, Cheng-Han Wu, Yi-Ying Liao, Chun-Ming Huang, Yen-Feng Lu, Ching-Yu Tsai, Tai-Lai Tung, Kuan-Fu Lin, Bo-Kang Lai, Yao-Syuan Lee, Tsyr-Rou Lin, Ming-Chao Tsai, Li-Hsuan Chiu
  • Publication number: 20250040198
    Abstract: A semiconductor device includes a substrate having a logic region and a high-voltage (HV) region, a first gate structure on the HV region, a first epitaxial layer and a second epitaxial layer adjacent to one side of the first gate structure, a first fin-shaped structure between the first epitaxial layer and the substrate, and a first contact plug between the first epitaxial layer and the second epitaxial layer. Preferably, the first gate structure includes a gate dielectric layer, top surfaces of the gate dielectric layer and the first fin-shaped structure are coplanar, and a bottom surface of the first epitaxial layer is lower than a bottom surface of the first contact plug.
    Type: Application
    Filed: October 16, 2024
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Cheng-Pu Chiu, Tzung-Ying Lee, Dien-Yang Lu, Chun-Kai Chao, Chun-Mao Chiou
  • Publication number: 20240247773
    Abstract: A package structure includes a carrier, a frame, and at least one photonic device. The carrier includes a substrate and a plurality of first metal pads and second metal pads. The substrate includes a first surface and a second surface that are opposite to each other. The first metal pads are disposed on the first surface. The second metal pads are disposed on the second surface. A thickness of each of the second metal pads is greater than that of each of the first metal pads. The frame is disposed on the carrier, and an accommodating space is formed between the frame and the carrier. The at least one photonic device is disposed in the accommodating space.
    Type: Application
    Filed: April 8, 2024
    Publication date: July 25, 2024
    Inventors: CHEN-HSIU LIN, CHENG-YING LEE, MING-SUNG TSAI
  • Patent number: 11959606
    Abstract: A package structure including a carrier, a photonic device, a supporting frame, and an encapsulant is provided. The photonic device is disposed on the carrier. The supporting frame is disposed on the carrier and surrounds the photonic device. The encapsulant covers the supporting frame and surrounds the photonic device.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 16, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chen-Hsiu Lin, Cheng-Ying Lee, Ming-Sung Tsai
  • Patent number: 11787332
    Abstract: A light-emitting device includes a substrate including circuit pads and a resin portion. A frame disposed on the substrate to form a first space, first to third light sources, and first and second encapsulants. The frame includes an outer wall and a first partition in the first space to form the first space as independent second and third spaces. A first and second light sources are disposed at the second space and provide first and second light beams respectively. A third light source is disposed at the third space and provides a third light beam. A first encapsulant is filled at the second space to seal the first and second light sources. A second encapsulant is filled at the third space to seal the third light source. The second encapsulant includes a first wavelength conversion material converting the third light beam into a fourth light beam.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: October 17, 2023
    Assignee: Lite-On Technology Corporation
    Inventors: Kai Yu Hsieh, Chih Chiang Kao, Cheng Ying Lee, Tsung Lin Lu
  • Publication number: 20220242305
    Abstract: A light-emitting device includes a substrate including circuit pads and a resin portion. A frame disposed on the substrate to form a first space, first to third light sources, and first and second encapsulants. The frame includes an outer wall and a first partition in the first space to form the first space as independent second and third spaces. A first and second light sources are disposed at the second space and provide first and second light beams respectively. A third light source is disposed at the third space and provides a third light beam. A first encapsulant is filled at the second space to seal the first and second light sources. A second encapsulant is filled at the third space to seal the third light source. The second encapsulant includes a first wavelength conversion material converting the third light beam into a fourth light beam.
    Type: Application
    Filed: December 14, 2021
    Publication date: August 4, 2022
    Applicant: Lite-On Technology Corporation
    Inventors: Kai Yu Hsieh, Chih Chiang Kao, Cheng Ying Lee, Tsung Lin Lu
  • Publication number: 20210301993
    Abstract: A package structure including a carrier, a photonic device, a supporting frame, and an encapsulant is provided. The photonic device is disposed on the carrier. The supporting frame is disposed on the carrier and surrounds the photonic device. The encapsulant covers the supporting frame and surrounds the photonic device.
    Type: Application
    Filed: March 30, 2021
    Publication date: September 30, 2021
    Inventors: CHEN-HSIU LIN, CHENG-YING LEE, MING-SUNG TSAI