Patents by Inventor Cheng-Ying Wu

Cheng-Ying Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250107037
    Abstract: The disclosure provides a liquid-cooling device and an electronic device. The liquid-cooling device includes an accommodation housing and a liquid-cooling assembly. The accommodation housing has an accommodation structure. The liquid-cooling assembly includes at least one liquid-cooling heat exchanger, a cold plate and a tubing. The at least one liquid-cooling heat exchanger is located in the accommodation structure. The cold plate is covered on the accommodation housing and covers the accommodation structure. The tubing is connected to the at least one liquid-cooling heat exchanger and penetrates through the cold plate.
    Type: Application
    Filed: December 26, 2023
    Publication date: March 27, 2025
    Inventors: Wen Hua Zhang, Cheng Ying Wu, SHIH CHANG CHEN, kuo-hua Peng, CHIEN-JUNG CHIU
  • Publication number: 20250081392
    Abstract: An immersion heat dissipation system having two circulations includes a tank body, a first working fluid, a liquid heat exchanger, a first circulation pipe unit, a first fluid driving unit, a gas transfer apparatus, a gas heat exchanger, a second circulation pipe unit, a second working fluid, and a second fluid driving unit. The tank body accommodates the first working fluid and the liquid heat exchanger immersed in the first working fluid. The first circulation pipe unit is in communication with the tank body to form a first circulation path. Through the second circulation pipe unit, the liquid heat exchanger is connected to the gas heat exchanger to form a second circulation path. The first working fluid and the second working fluid are driven by the first fluid driving unit and the second fluid driving unit, respectively, to flow toward the liquid heat exchanger for heat dissipation.
    Type: Application
    Filed: February 16, 2024
    Publication date: March 6, 2025
    Inventors: Wen-Hua ZHANG, Cheng-Ying WU, Kuo-Hua PENG, Chien-Jung CHIU
  • Publication number: 20240397576
    Abstract: The application provides a wireless communication method and a wireless communication device. A part of payload is pre-fetched from a host to a data buffer under a store-and-forward mode before transmission begins. When data transmission begins, the part of the payload pre-fetched in the data buffer is transmitted to an antenna. A remaining part of the payload is fetched to the data buffer under a cut-through mode for payload transmission, wherein the remaining part of the payload is sent from the data buffer to the antenna for radiation.
    Type: Application
    Filed: May 14, 2024
    Publication date: November 28, 2024
    Inventors: Hao-Hua KANG, Hui-Ping TSENG, Cheng-Ying WU, Chih-Chun KUO, Shu-Min CHENG, Chi-Han HUANG, Yang-Hung PENG, Jyh-Ding HU, Chih-Pin CHU, Chu-Ling CHANG, Yen-Hsiung TSENG, Chi-Fu KOH, Yen CHUANG
  • Publication number: 20240373493
    Abstract: A method for performing mode switching management in multi-link operation (MLO) architecture and associated apparatus are provided. The method applicable to a wireless transceiver device communicating with another device within a wireless communications system may include: executing a mode switching procedure regarding a predetermined MLO-related mode in a first protection period dedicated to the mode switching procedure, so that no other transmission request is received during the first protection period, where the first protection period is equal to or longer than the time spent on executing the mode switching. The mode switching procedure may include sending a protection indication in a first communications frame from the wireless transceiver device to the other device that informs the other device not to send any transmission request, or the wireless transceiver device may perform information exchange in advance to notify the other device of mode switch processing delay as the first protection period.
    Type: Application
    Filed: May 2, 2024
    Publication date: November 7, 2024
    Applicant: MEDIATEK INC.
    Inventors: Hao-Hua Kang, Cheng-Ying Wu
  • Publication number: 20240244007
    Abstract: A reordering method performed by a receiving apparatus is provided. The receiving apparatus may receive a first PPDU from a transmitting apparatus, wherein the first PPDU includes a plurality of MPDUs, and the MPDUs correspond to the same BA window. The receiving apparatus may determine a traffic that each of the MPDUs belongs to according to an MPDU identification, wherein traffics that the plurality of MPDUs belonging to include a first traffic and a second traffic which is different from the first traffic. The receiving apparatus may perform a reordering operation for the MPDUs belonging to the first traffic, and a reordering operation for the MPDUs belonging to the second traffic, respectively. The receiving apparatus may transmit a BA frame in response to the first PPDU to the transmitting apparatus, wherein the BA frame includes information for indicating whether the MPDUs in the first PPDU have been successfully received.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Inventors: Chi-Han HUANG, Yen-Hsiung TSENG, Cheng-Ying WU, Wei-Wen LIN
  • Publication number: 20240163932
    Abstract: A multi-link operation (MLO) transmission method is provided. The MLO transmission method may be applied to an apparatus. The MLO transmission method may include the following steps. A plurality of station (STA) modules of the apparatus may each perform a respective backoff procedure. Each STA module may correspond to a different link. An MLO control circuit of the apparatus or a first STA module of the plurality of STA modules may determine whether to perform a synchronous transmission (TX) for a first STA module and at least one of other STA modules in response to a first backoff counter of the first STA module reaching 0.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Inventors: Hao-Hua KANG, Chih-Chun KUO, Cheng-Ying WU, Yang-Hung PENG
  • Publication number: 20240163785
    Abstract: A method for performing wireless communication in MLO architecture is applicable to an AP MLD connected with a non-AP MLD through multiple links. The multiple links include at least a first link and a second link, the non-AP MLD operates in ML-SMPS mode. The method includes transmitting an initial control frame to the non-AP MLD via the first link, to trigger at least one link of the multiple links to be activated at the non-AP MLD to support a reception with respective negotiated number of spatial streams, receiving a response frame via the first link in response to the transmission of the initial control frame, and initiating frame exchange between the AP MLD and the non-AP MLD via a target link of the at least one link. The target link is selected from the at least one link according to the response frame. The first link is a primary link.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 16, 2024
    Applicant: MEDIATEK INC.
    Inventors: Hao-Hua Kang, Cheng-Ying Wu, Chien-Fang Hsu, Chih-Chun Kuo
  • Publication number: 20240163947
    Abstract: A method for multi-link operation (MLO) is provided. The method for MLO may be applied to an apparatus. The method for MLO may include the following steps. A multi-chip controller of the apparatus may assign different data to a plurality of chips of the apparatus, wherein each chip corresponds to one link of multi-links. Each chip may determine whether transmission of the assigned data has failed. A first chip of the chips may transmit the assigned data to an access point (AP) in response to the first chip determining that the transmission of the assigned data has not failed.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: Cheng-Ying WU, Wei-Wen LIN, Shu-Min CHENG, Hui-Ping TSENG, Chi-Han HUANG, Chih-Chun KUO, Yang-Hung PENG, Hao-Hua KANG
  • Publication number: 20230188266
    Abstract: One wireless communication method includes: receiving a request action frame; and in response to the request action frame, generating and sending an acknowledgement (ACK) control frame that is configured to serve as a response action frame for the request action frame, wherein the response action frame is not solicited by the request action frame. Another wireless communication method includes: receiving a request action frame; and in response to the request action frame, generating and sending an acknowledgement (ACK) control frame and a time-constrained response action frame following the ACK control frame, wherein the time-constrained response action frame is solicited by the request action frame.
    Type: Application
    Filed: November 24, 2022
    Publication date: June 15, 2023
    Applicant: MEDIATEK INC.
    Inventors: Chien-Fang Hsu, Cheng-Ying Wu, Chao-Wen Chou, Yongho Seok
  • Patent number: 11380694
    Abstract: A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 5, 2022
    Assignee: YIELD MICROELECTRONICS CORP.
    Inventors: Cheng-Ying Wu, Yu-Ting Huang, Wen-Chien Huang
  • Publication number: 20210248603
    Abstract: A block chain-based transaction processing method and apparatus are disclosed, in which an intermediate computing device receives and validates a first block record from, and generates and sends a second block record to, a first computing device; receives a third block record generated by a second computing device after validating the second block record from the intermediate computing device; generates and sends a fourth block record to the second computing device after validating the third block record, receives from the first computing device a fifth block record generated by the first computing device after validating the fourth block record from the intermediate computing device; receives from the second computing device a sixth block record generated by the second computing device after validating the fifth block record from the intermediate computing device; and broadcasts the first to sixth block records to other computing devices after validating the fifth and sixth block records.
    Type: Application
    Filed: April 26, 2021
    Publication date: August 12, 2021
    Inventors: Ching Song WU, Chun-Wei YU, Chih Sheng WANG, Yi Hung LIANG, Cheng-Ying WU
  • Publication number: 20210242223
    Abstract: A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.
    Type: Application
    Filed: March 4, 2020
    Publication date: August 5, 2021
    Inventors: CHENG-YING WU, YU-TING HUANG, WEN-CHIEN HUANG
  • Publication number: 20210169319
    Abstract: In a first example, a nasopharyngeal mirror device includes a handle, a convex mirror configured to move with respect to the handle, and an anti-fogging device configured to reduce condensation on the convex mirror. In a second example, a method includes inserting a convex mirror of a nasopharyngeal mirror device into a mouth of a patient and moving the convex mirror with respect to a handle of the nasopharyngeal mirror device such that a tissue of interest of the patient is viewable within the convex mirror. The method also includes capturing an image of the tissue of interest with a camera of the nasopharyngeal mirror device while the tissue of interest is viewable within the convex mirror.
    Type: Application
    Filed: December 2, 2020
    Publication date: June 10, 2021
    Inventors: Sanjay Parikh, Ryan King, Nisha Pradhan, Ga Won Kim, Koustubh Muluk, Cheng-Ying Wu, Sarah Rudberg
  • Publication number: 20210167074
    Abstract: An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.
    Type: Application
    Filed: January 21, 2020
    Publication date: June 3, 2021
    Inventors: CHENG-YING WU, CHENG-YU CHUNG, WEN-CHIEN HUANG
  • Patent number: 11004857
    Abstract: An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: May 11, 2021
    Assignee: Yield Microelectronics Corp.
    Inventors: Cheng-Ying Wu, Cheng-Yu Chung, Wen-Chien Huang
  • Publication number: 20210104279
    Abstract: A single-gate multiple-time programming non-volatile memory array and an operating method thereof are provided, wherein the single-gate non-volatile memory array has bit lines, common source line groups, and sub-memory arrays. In each sub-memory array, a first memory cell is connected with a first bit line and one common source line of a first common source line group. The second memory cell is connected with the first bit line and the other common source line of the first common source line group. The first and second memory cells are operation memory cells and symmetrically arranged at the same side of the first bit line. The minimum control voltages and elements during operating are involved to greatly reduce the area, control lines and the cost thereof.
    Type: Application
    Filed: December 10, 2019
    Publication date: April 8, 2021
    Inventors: CHENG-YING WU, WEI-TUNG LO, WEN-CHIEN HUANG
  • Patent number: 10854297
    Abstract: An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 1, 2020
    Assignee: Yield Microelectronics Corp.
    Inventors: Cheng-Ying Wu, Cheng-Yu Chung, Wen-Chien Huang
  • Patent number: 10050863
    Abstract: A network communication system, a software-defined network controller and a routing method thereof are provided. The routing method is adapted to the software-defined network controller. The routing method includes the following steps: determining a first root switch corresponding to at least one first service cluster according to service chaining information, wherein each of the at least one first service cluster includes at least one service node for providing a first service; determining first routing path information for routing a packet flow from a first target switch to the first root switch; and configuring first group entry information for the first root switch according to cluster information of the at least one first service cluster, wherein the first group entry information is for performing a first routing path selection of the packet flow corresponding to the first service by the first root switch.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: August 14, 2018
    Assignee: National Chiao Tung University
    Inventors: Ying-Dar Lin, Cheng-Ying Wu, Po-Ching Lin, Yuan-Cheng Lai
  • Publication number: 20170207994
    Abstract: A network communication system, a software-defined network controller and a routing method thereof are provided. The routing method is adapted to the software-defined network controller. The routing method includes the following steps: determining a first root switch corresponding to at least one first service cluster according to service chaining information, wherein each of the at least one first service cluster includes at least one service node for providing a first service; determining first routing path information for routing a packet flow from a first target switch to the first root switch; and configuring first group entry information for the first root switch according to cluster information of the at least one first service cluster, wherein the first group entry information is for performing a first routing path selection of the packet flow corresponding to the first service by the first root switch.
    Type: Application
    Filed: April 21, 2016
    Publication date: July 20, 2017
    Inventors: Ying-Dar Lin, Cheng-Ying Wu, Po-Ching Lin, Yuan-Cheng Lai
  • Patent number: 9318208
    Abstract: A method for operating a small-area EEPROM array is disclosed. The small-area EEPROM array comprises bit lines, word lines, common source lines, and sub-memory arrays. The bit lines are divided into bit line groups. The word lines include a first word line. The common source lines include a first common source line. Each sub-memory array includes a first, second, third and fourth memory cells, which are connected with two bit line groups, a word line and a common source line. The first and second memory cells are symmetric. The third and fourth memory cells are symmetric. The group of the first and second memory cells and the group of the third and fourth memory cells are respectively positioned at two sides of the first common source line. The method operates all operation memory cells and uses special biases to program or erase memory cells massively in a single operation.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: April 19, 2016
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Wen-Chien Huang, Ya-Ting Fan, Yang-Sen Yeh, Cheng-Ying Wu