Patents by Inventor Cheng-Ying Yeh

Cheng-Ying Yeh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113262
    Abstract: A light-emitting device includes: a semiconductor stack, including a first semiconductor layer, an active region and a second semiconductor layer; a first contact electrode and a second contact electrode formed on the semiconductor stack, wherein the first contact electrode includes a first contact part formed on the first semiconductor layer and the second contact electrode includes a second contact part formed on the second semiconductor layer; an insulating stack formed on the semiconductor stack, including an opening on the second contact part; a first electrode pad and a second electrode pad formed on the insulating stack, wherein the second electrode pad filled in the opening and connecting the second contact part; wherein the second electrode pad includes an upper surface, and the upper surface includes a platform area and a depression area on the second contact part; wherein the platform area has a maximum height relative to other areas of the upper surface; wherein an area of a projection of the plat
    Type: Application
    Filed: September 1, 2023
    Publication date: April 4, 2024
    Inventors: Hsin-Ying WANG, Hui-Chun YEH, Jhih-Yong YANG, Chen OU, Cheng-Lin LU
  • Patent number: 11935890
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
  • Publication number: 20100188584
    Abstract: A depth calculating method is provided for calculating corresponding depth data in response to frame data, which includes macroblocks. The depth calculating method includes the following steps. First, a type of video is decided according to a video content. A motion vector is obtained from decompressed video information and is modified according to a shot change detection and camera motion data. Then, multiple pieces of macroblock motion parallax data respectively corresponding to the macroblocks are found according to motion vector data of the modified macroblocks. Thereafter, the depth data corresponding to the frame data is calculated according to the pieces of macroblock motion parallax data, variance data, contrast data and texture gradient data.
    Type: Application
    Filed: July 28, 2009
    Publication date: July 29, 2010
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kai-Che Liu, Wen-Chao Chen, Jinn-Cherng Yang, Wen-Nung Lie, Guo-Shiang Lin, Cheng-Ying Yeh