Patents by Inventor Cheng-Yu Chang
Cheng-Yu Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127988Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 48% to 55%. The conductive filler has a metal-ceramic compound.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Inventors: HSIU-CHE YEN, YUNG-HSIEN CHANG, CHENG-YU TUNG, Chia-Yuan Lee, CHEN-NAN LIU, Yao-Te Chang, FU-HUA CHU
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Publication number: 20240127989Abstract: An over-current protection device includes a first metal layer, a second metal layer and a heat-sensitive layer laminated therebetween. The heat-sensitive layer exhibits a positive temperature coefficient (PTC) characteristic and includes a first polymer and a conductive filler. The first polymer consists of polyvinylidene difluoride (PVDF), and PVDF exists in different phases such as ?-PVDF, ?-PVDF and ?-PVDF. The total amount of ?-PVDF, ?-PVDF and ?-PVDF is calculated as 100%, and the amount of ?-PVDF accounts for 33% to 42%.Type: ApplicationFiled: January 25, 2023Publication date: April 18, 2024Inventors: CHIA-YUAN LEE, CHENG-YU TUNG, HSIU-CHE YEN, CHEN-NAN LIU, YUNG-HSIEN CHANG, YAO-TE CHANG, FU-HUA CHU
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Publication number: 20240120239Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Inventors: Cheng-Wei CHANG, Chi-Yu CHOU, Lun-Kuang TAN, Shuen-Shin LIANG
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Patent number: 11955329Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: GrantFiled: April 28, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Patent number: 11955535Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.Type: GrantFiled: July 26, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20240113143Abstract: Various embodiments of the present disclosure are directed towards an imaging device including a first image sensor element and a second image sensor element respectively comprising a pixel unit disposed within a semiconductor substrate. The first image sensor element is adjacent to the second image sensor element. A first micro-lens overlies the first image sensor element and is laterally shifted from a center of the pixel unit of the first image sensor element by a first lens shift amount. A second micro-lens overlies the second image sensor element and is laterally shifted from a center of the pixel unit of the second image sensor element by a second lens shift amount different from the first lens shift amount.Type: ApplicationFiled: January 6, 2023Publication date: April 4, 2024Inventors: Cheng Yu Huang, Wen-Hau Wu, Chun-Hao Chuang, Keng-Yu Chou, Wei-Chieh Chiang, Chih-Kung Chang
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Patent number: 11948879Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.Type: GrantFiled: July 27, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240105787Abstract: Embodiments of the present disclosure provide a method of forming a contact opening using selective ALE operations to remove ILD layer along an upper profile of a source/drain region, and then form a source/drain contact feature having a concave bottom profile with increased contact area.Type: ApplicationFiled: February 1, 2023Publication date: March 28, 2024Inventors: Cheng-Wei CHANG, Shahaji B. MORE, Chi-Yu CHOU, Yueh-Ching PAI
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Publication number: 20240088182Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
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Publication number: 20240086609Abstract: A system including a processor configured to perform generating a plurality of different layout blocks; selecting, among the plurality of layout blocks, layout blocks corresponding to a plurality of blocks in a floorplan of a circuit; combining the selected layout blocks in accordance with the floorplan into a layout of the circuit; and storing the layout of the circuit in a cell library or using the layout of the circuit to generate a layout for an integrated circuit (IC) containing the circuit. Each of the plurality of layout blocks satisfies predetermined design rules and includes at least one of a plurality of different first block options associated with a first layout feature, and at least one of a plurality of different second block options associated with a second layout feature different from the first layout feature.Type: ApplicationFiled: February 16, 2023Publication date: March 14, 2024Inventors: Cheng-YU LIN, Chia Chun WU, Han-Chung CHANG, Chih-Liang CHEN
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Patent number: 11923386Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.Type: GrantFiled: April 24, 2023Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Yu Chou, Chun-Hao Chuang, Kazuaki Hashimoto, Wei-Chieh Chiang, Cheng Yu Huang, Wen-Hau Wu, Chih-Kung Chang
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Publication number: 20240071656Abstract: A circuit protection device includes a first temperature sensitive resistor, a second temperature sensitive resistor, an electrically insulating multilayer, a first and second electrode layer, and at least one external electrode. The first temperature sensitive resistor and the second temperature sensitive resistor are electrically connected in parallel, and have a first upper electrically conductive layer and a second lower electrically conductive layer, respectively. The electrically insulating multilayer includes an upper insulating layer, a middle insulating layer, and a lower insulating layer. The upper insulating layer is between the first upper electrically conductive layer and the first electrode layer. The middle layer is laminated between the first temperature sensitive resistor and the second temperature sensitive resistor. The lower insulating layer is between the second lower electrically conductive layer and the second electrode layer.Type: ApplicationFiled: January 13, 2023Publication date: February 29, 2024Inventors: Chien Hui WU, Yung-Hsien CHANG, Cheng-Yu TUNG, Ming-Hsun LU, Yi-An SHA
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Patent number: 11915994Abstract: A package structure is provided. The package structure includes a semiconductor die and a thermoelectric structure disposed on the semiconductor die. The thermoelectric structure includes P-type semiconductor blocks, N-type semiconductor blocks and metal pads. The P-type semiconductor blocks and the N-type semiconductor blocks are arranged in alternation with the metal pads connecting the P-type semiconductor blocks and the N-type semiconductor blocks. When a current flowing through one of the N-type semiconductor block, one of the metal pad, and one of the P-type semiconductor block in order, the metal pad between the N-type semiconductor block and the P-type semiconductor block forms a cold junction which absorbs heat generated by the semiconductor die.Type: GrantFiled: August 12, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yen Hsieh, Chih-Horng Chang, Chung-Yu Lu
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Patent number: 11759688Abstract: An artificial shuttlecock, a feather and a preparation method thereof are provided. The feather includes a connecting portion, a first portion, a second portion and a concave. The first portion and the second portion are disposed on the opposite sides of the connecting portion. The concave is located at an outer edge of the second portion. The concave is formed by the following steps of: defining an overlapped outline, which is the outline of the adjacent feather overlapping on the second portion; defining a reference point, which is a point where the overlapped outline is closest to the connecting portion; defining a shifting reference line, which passes through the reference point and is parallel to the connecting portion; defining a reference outline, which is located outside the shifting reference line; and cutting the reference outline to form the concave.Type: GrantFiled: December 28, 2021Date of Patent: September 19, 2023Assignee: Victor Rackets Industrial Corp.Inventors: Shu-Jung Chen, Tzu-Wei Wang, Hsin-Chen Wang, Cheng-Yu Chang
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Publication number: 20220219057Abstract: An artificial shuttlecock, a feather and a preparation method thereof are provided. The feather includes a connecting portion, a first portion, a second portion and a concave. The first portion and the second portion are disposed on the opposite sides of the connecting portion. The concave is located at an outer edge of the second portion. The concave is formed by the following steps of: defining an overlapped outline, which is the outline of the adjacent feather overlapping on the second portion; defining a reference point, which is a point where the overlapped outline is closest to the connecting portion; defining a shifting reference line, which passes through the reference point and is parallel to the connecting portion; defining a reference outline, which is located outside the shifting reference line; and cutting the reference outline to form the concave.Type: ApplicationFiled: December 28, 2021Publication date: July 14, 2022Inventors: Shu-Jung Chen, Tzu-Wei Wang, Hsin-Chen Wang, Cheng-Yu Chang
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Patent number: 10814187Abstract: The present invention discloses a badminton racket, which includes a frame, a grip, a cap and a shaft. The grip includes a gripping portion, a sleeved portion, and a fastening element connected to the gripping portion. The sleeved portion has a first top surface and a first opening. The fastening element is connected to the first top surface, and the fastening element extends from the first opening to the inside of the gripping portion. The cap is sleeved onto the sleeved portion and has a second top surface and a second opening. There is a spacing length between the first top surface and the second top surface, and the cap has a cap length. The ratio of the spacing length to the cap length is between 0.39 and 0.83. One end of the shaft is connected to the frame, and another end is inserted into the fastening element.Type: GrantFiled: October 4, 2019Date of Patent: October 27, 2020Assignee: Victor Rackets Industrial Corp.Inventors: Shu-Jung Chen, Tzu-Wei Wang, Hsin-Chen Wang, Cheng-Yu Chang
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Patent number: 10814196Abstract: The present disclosure discloses a synthetic shuttlecock, which includes a base portion, a plurality of stems, and a plurality of feathers. One end of each of the stems is inserted into the base portion. Two of the feathers are connected to one of the stems. A connecting portion is formed on the stem, respectively. Each of the feathers has a first length and a first width. Each of the feathers has two holes, the two holes are located on the two sides of the connecting portion respectively, and the holes are close to a front end of the connecting portion. Each of the holes has a second length and a second width. The ratio of the second length to the first length is between 0.22 and 0.31, and the ratio of the second width to the first width is between 0.06 and 0.28.Type: GrantFiled: October 23, 2019Date of Patent: October 27, 2020Assignee: Victor Rackets Industrial Corp.Inventors: Shu-Jung Chen, Tzu-Wei Wang, Hsin-Chen Wang, Cheng-Yu Chang
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Publication number: 20200206595Abstract: The present disclosure discloses a synthetic shuttlecock, which includes a base portion, a plurality of stems, and a plurality of feathers. One end of each of the stems is inserted into the base portion. Two of the feathers are connected to one of the stems. A connecting portion is formed on the stem, respectively. Each of the feathers has a first length and a first width. Each of the feathers has two holes, the two holes are located on the two sides of the connecting portion respectively, and the holes are close to a front end of the connecting portion. Each of the holes has a second length and a second width. The ratio of the second length to the first length is between 0.22 and 0.31, and the ratio of the second width to the first width is between 0.06 and 0.28.Type: ApplicationFiled: October 23, 2019Publication date: July 2, 2020Inventors: SHU-JUNG CHEN, TZU-WEI WANG, HSIN-CHEN WANG, CHENG-YU CHANG
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Publication number: 20200139204Abstract: The present invention discloses a badminton racket, which includes a frame, a grip, a cap and a shaft. The grip includes a gripping portion, a sleeved portion, and a fastening element connected to the gripping portion. The sleeved portion has a first top surface and a first opening. The fastening element is connected to the first top surface, and the fastening element extends from the first opening to the inside of the gripping portion. The cap is sleeved onto the sleeved portion and has a second top surface and a second opening. There is a spacing length between the first top surface and the second top surface, and the cap has a cap length. The ratio of the spacing length to the cap length is between 0.39 and 0.83. One end of the shaft is connected to the frame, and another end is inserted into the fastening element.Type: ApplicationFiled: October 4, 2019Publication date: May 7, 2020Inventors: Shu-Jung Chen, Tzu-Wei Wang, Hsin-Chen Wang, Cheng-Yu Chang
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Publication number: 20170242744Abstract: A method for performing data scrubbing management in a storage system and an associated apparatus are provided. The method includes: detecting whether a system event within at least one predetermined system event occurs to generate a detection result; and selectively triggering a data scrubbing operation in the storage system according to the detection result. Each predetermined system event within the predetermined system event is not generated via scheduling settings, is not generated via prior scheduling settings corresponding to a fixed period, and the scrubbing operation is a non-scheduling event triggered scrubbing operation.Type: ApplicationFiled: February 18, 2017Publication date: August 24, 2017Inventors: Yu-Ting Wang, Cheng-Yu Chang