Patents by Inventor Cheng-Yu Chung

Cheng-Yu Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210000873
    Abstract: The present technology relates generally to compositions and methods for creating recombinant T cell receptor (TCR) libraries and methods of their therapeutic use. The compositions and methods of the present technology are useful for rapid isolation of antigen-specific TCR repertoires as personalized, targeted therapies for cancer and viral infection.
    Type: Application
    Filed: February 27, 2019
    Publication date: January 7, 2021
    Applicant: University of Kansas
    Inventors: Brandon DEKOSKY, Cheng-Yu CHUNG
  • Patent number: 10854297
    Abstract: An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 1, 2020
    Assignee: Yield Microelectronics Corp.
    Inventors: Cheng-Ying Wu, Cheng-Yu Chung, Wen-Chien Huang
  • Publication number: 20200327944
    Abstract: The present invention discloses a method of fast erasing an EEPROM with low-voltages. The EEPROM includes a transistor structure is formed in a semiconductor substrate and the transistor structure includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for erasing. Moreover, the source or the drain is floated during erasing to achieve rapid erasing for a large number of memory cells. In addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 15, 2020
    Inventors: HSIN-CHANG LIN, CHENG-YU CHUNG, WEN-CHIEN HUANG
  • Patent number: 10685716
    Abstract: A method of fast erasing a low-current EEPROM array. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The source or the drain is floated during erasing to perform the fast bytes-erasing with low current, low voltage and low cost.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: June 16, 2020
    Assignee: YIELD MICROELECTRONICS CORP.
    Inventors: Hsin-Chang Lin, Cheng-Yu Chung, Wen-Chien Huang
  • Patent number: 10673813
    Abstract: The present invention provides a method for NAT traversal in VPN so that the VPN can detect the rule of port allocation for NAT outside the VPN to achieve NAT traversal. The communication structure according to the present invention includes a public network, a client network, a destination network, a first NAT, a second NAT. A DNAT-T proxy server is installed between the first NAT and the second NAT and has the function for the VPN to conduct a plurality of (N times) registrations before sending data out to detect the rule for NAT port allocation of the DNAT-T proxy server, and then inform the next NAT port allocation to the other side of the VPN so as to achieve NAT traversal for the data packets in VPN.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 2, 2020
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Hsueh Ming Hang, Shaw Hwa Hwang, Cheng Yu Yeh, Bing Chih Yao, Kuan Lin Chen, Yao Hsing Chung, Shun Chieh Chang, Chi Jung Huang, Li Te Shen, Ning Yun Ku, Tzu Hung Lin, Ming Che Yeh
  • Patent number: 10643708
    Abstract: A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: May 5, 2020
    Assignee: Yield Microelectronics Corp.
    Inventors: Hsin-Chang Lin, Cheng-Yu Chung, Wen-Chien Huang
  • Publication number: 20200118631
    Abstract: A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 16, 2020
    Inventors: HSIN-CHANG LIN, CHENG-YU CHUNG, WEN-CHIEN HUANG
  • Patent number: 10622509
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Patent number: 10622510
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: April 14, 2020
    Assignee: Ingentec Corporation
    Inventors: Ya-Li Chen, Chi-Ming Wang, Chia-Wei Tu, Cheng-Yu Chung, Hsiang-An Feng
  • Publication number: 20200058523
    Abstract: A gas etching device includes an upper cover having a first gas exhausting channel that surrounds a first accommodation space. A lower cover has a second accommodation space where a wafer is located. The lower cover can connect with the upper cover. A gas jetting element is arranged in the first accommodation space to communicate with the upper cover. The gas jetting element receives etching gas from outside the upper cover and jets the etching gas in the first accommodation space and the second accommodation space to react with the wafer. The reacted etching gas is exhausted through the first gas exhausting channel. The first gas entering channel continues receives high-pressure gas from outside the upper cover and transmits the high-pressure gas to the second gas entering channel, so as to avoid leaking the etching gas.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 20, 2020
    Inventors: YA-LI CHEN, HSIANG-AN FENG, CHENG-YU CHUNG
  • Patent number: 10506405
    Abstract: A connecting method includes broadcasting, through a first transmission component of a first connection device, a device name of the first connection device and an address of the first connection device; transmitting, through a second transmission component of the first connection device, identification information of the first connection device to a second connection device; performing, through the second connection device, a scanning procedure to acquire the device name and the address of the first connection device; and building, through the second connection device, a connection with the first connection device according to the identification information of the first connection device, the device name of the first connection device, and the address of the first connection device.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: December 10, 2019
    Assignee: HTC Corporation
    Inventors: Chia-Wei Chen, Cheng-Kang Lin, Cheng-Yu Chung
  • Publication number: 20190238503
    Abstract: The present invention provides a method for NAT traversal in VPN so that the VPN can detect the rule of port allocation for NAT outside the VPN to achieve NAT traversal. The communication structure according to the present invention includes a public network, a client network, a destination network, a first NAT, a second NAT. A DNAT-T proxy server is installed between the first NAT and the second NAT and has the function for the VPN to conduct a plurality of (N times) registrations before sending data out to detect the rule for NAT port allocation of the DNAT-T proxy server, and then inform the next NAT port allocation to the other side of the VPN so as to achieve NAT traversal for the data packets in VPN.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 1, 2019
    Inventors: Hsueh Ming HANG, Shaw Hwa HWANG, Cheng Yu YEH, Bing Chih YAO, Kuan Lin CHEN, Yao Hsing CHUNG, Shun Chieh CHANG, Chi Jung HUANG, Li Te SHEN, Ning Yun KU, Tzu Hung LIN, Ming Che YEH
  • Publication number: 20190189836
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Application
    Filed: December 18, 2017
    Publication date: June 20, 2019
    Inventors: YA-LI CHEN, CHI-MING WANG, CHIA-WEI TU, CHENG-YU CHUNG, HSIANG-AN FENG
  • Publication number: 20190189837
    Abstract: A vertical type light emitting diode die and a method for fabricating the same is disclosed. A growth substrate is provided and an epitaxial layer is formed on the growth substrate. A metallic combined substrate is connected to the epitaxial layer. Then, the growth substrate is removed. Electrode units are formed on the top surface of the epitaxial layer. The epitaxial layer is divided into epitaxial dies according to the number of the plurality of electrode units. Each vertical type light emitting diode die formed in the abovementioned way includes the metallic combined substrate having a first metal layer and second metal layers. The first metal layer is combined with the two second metal layers by cutting, vacuum heating, and polishing, so as to enable the metallic combined substrate to have a high coefficient of thermal conductivity, a low coefficient of thermal expansion, and initial magnetic permeability.
    Type: Application
    Filed: June 19, 2018
    Publication date: June 20, 2019
    Inventors: YA-LI CHEN, CHI-MING WANG, CHIA-WEI TU, CHENG-YU CHUNG, HSIANG-AN FENG
  • Patent number: 10034323
    Abstract: A control method, suitable for a host device including a Bluetooth low energy communication circuit, includes following operations. A high priority list is obtained. The high priority list includes information about at least one first peripheral device. The BLE communication circuit is triggered to perform a first scan to search for any peripheral device around the host device. A first search result of the first scan is compared with the high priority list. In response to that the first search result covers all of the at least one first peripheral device in the high priority list, the BLE communication circuit is triggered to stop the first scan. The BLE communication circuit is triggered to communicate with the at least one first peripheral device found in the first scan.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: July 24, 2018
    Assignee: HTC Corporation
    Inventors: Jing-Lung Wu, Cheng-Yu Chung, Kai-Hsiu Chen
  • Publication number: 20180098368
    Abstract: A control method, suitable for a host device including a Bluetooth low energy communication circuit, includes following operations. A high priority list is obtained. The high priority list includes information about at least one first peripheral device. The BLE communication circuit is triggered to perform a first scan to search for any peripheral device around the host device. A first search result of the first scan is compared with the high priority list. In response to that the first search result covers all of the at least one first peripheral device in the high priority list, the BLE communication circuit is triggered to stop the first scan. The BLE communication circuit is triggered to communicate with the at least one first peripheral device found in the first scan.
    Type: Application
    Filed: March 30, 2017
    Publication date: April 5, 2018
    Inventors: Jing-Lung WU, Cheng-Yu CHUNG, Kai-Hsiu CHEN
  • Publication number: 20180097689
    Abstract: A connecting method includes broadcasting, through a first transmission component of a first connection device, a device name of the first connection device and an address of the first connection device; transmitting, through a second transmission component of the first connection device, identification information of the first connection device to a second connection device; performing, through the second connection device, a scanning procedure to acquire the device name and the address of the first connection device; and building, through the second connection device, a connection with the first connection device according to the identification information of the first connection device, the device name of the first connection device, and the address of the first connection device.
    Type: Application
    Filed: March 27, 2017
    Publication date: April 5, 2018
    Inventors: Chia-Wei CHEN, Chung-Kang LIN, Cheng-Yu CHUNG
  • Patent number: 9530652
    Abstract: The present invention relates to a method of producing patterned silver nanowire, comprising: coating a photosensitive polyamide acid polymer solution on a silica substrate and dried; using a photomask to paste on the photosensitive polyamic acid and illuminates by ultraviolet; using a developer to obtain a patterned polyamide acid template; coating a metal nanowire suspension on the patterned template; and removing the metal nanowire outside of the patterned polyamic acid. The present invention also discloses an electrode using the patterned metal nanowire and a transistor using the patterned metal nanowire electrode.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: December 27, 2016
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Hsuan-Chun Chang, Cheng-Yu Chung, Wen-Chang Chen
  • Publication number: 20160218009
    Abstract: The present invention relates to a method of producing patterned silver nanowire, comprising: coating a photosensitive polyamide acid polymer solution on a silica substrate and dried; using a photomask to paste on the photosensitive polyamic acid and illuminates by ultraviolet; using a developer to obtain a patterned polyamide acid template; coating a metal nanowire suspension on the patterned template; and removing the metal nanowire outside of the patterned polyamic acid. The present invention also discloses an electrode using the patterned metal nanowire and a transistor using the patterned metal nanowire electrode.
    Type: Application
    Filed: April 24, 2015
    Publication date: July 28, 2016
    Inventors: Hsuan-Chun CHANG, Cheng-Yu CHUNG, Wen-Chang CHEN
  • Publication number: 20140195839
    Abstract: A method and apparatus for performing wake-up event management and an associated computer program product are provided, where the method is applied to an electronic device. The method includes the steps of: classifying a plurality of wake-up events of the electronic device according to at least one predetermined rule, wherein a specific wake-up event of the plurality of wake-up events is classified to be a triggering event, and one or more other wake-up events of the plurality of wake-up events are classified to be grouping events; arranging the grouping events as a group corresponding to the triggering event by setting wake-up time of each of the grouping events to be equivalent to that of the triggering event, for triggering the grouping events by utilizing the triggering event; and when the wake-up time of the triggering event is reached, performing operations corresponding to the triggering event and the grouping events, respectively.
    Type: Application
    Filed: September 6, 2013
    Publication date: July 10, 2014
    Applicant: HTC Corporation
    Inventors: Hsin-Ti Chueh, Chen-Huang Fan, Chien-Nan Lin, Chi-Yang Chen, Chi-Leng Wang, Cheng-Yu Chung