Abstract: Disclosure is a compound with one or more arm(s) for drug conjugation and a conjugate including the compound so as to provide high drug-to-moiety ratio and conjugate more drugs to the conjugate.

Abstract: An examining method for a coating layer on a wafer is provided, including providing an incident light to the coating layer and generating a reflecting light after the coating layer receives the incident light. A spectral analysis of the reflecting light is then generated and compared with a first reference waveform to determine a material of the coating layer. Moreover, the spectral analysis may be further compared with a second reference waveform to determine a thickness of the coating layer. The incident light and reflecting light are provided and received by a spectroscope which is placed above on the wafer to provide perpendicular optical paths to the coating layer on the upper surface of the wafer. By employing the disclosed method, the material and thickness of the coating layer on the wafer can be examined and further classified so as to enhance the conventional efficiency in the prior arts.

Abstract: A level shifting circuit includes a first-type level shifter, a second-type level shifter and a controller. The controller is connected to the output terminal of the first-type level shifter and the output terminal of the second-type level shifter. The level shifting circuit can be operated in different modes. In a standby mode, the logic level state of an output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the first-type level shifter. In a non-standby mode, the logic level state of the output signal from the level shifting circuit is determined according to the logic level state of a shifted signal from the second-type level shifter.

Abstract: The present technology relates generally to compositions and methods for creating recombinant T cell receptor (TCR) libraries and methods of their therapeutic use. The compositions and methods of the present technology are useful for rapid isolation of antigen-specific TCR repertoires as personalized, targeted therapies for cancer and viral infection.

Abstract: A laser diode includes an original substrate having a substrate coefficient of thermal expansion, an epitaxy structure formed on the original substrate, and a composite multi-layer metal board disposed below the original substrate and at least including a first metal layer and a second metal layer. The first metal layer and the second metal layer are stacked, a material of the first metal layer is different from a material of the second metal layer, and the composite multi-layer metal board has a modified coefficient of thermal expansion. The original substrate has an initial thickness as the epitaxy structure is grown thereon, the original substrate is thinned to a combining thickness for attaching the composite multi-layer metal board, and the modified coefficient of thermal expansion of the composite multi-layer metal board is proximate to the substrate coefficient of thermal expansion.

Abstract: A magnetic light-emitting structure and fabrication method for manufacturing a magnetic light-emitting element are provided. The fabrication method comprises providing a magnetic metal composite substrate, wherein a second metal layer is respectively disposed on an upper and lower surface of a first metal layer; forming a connecting metal layer, an epitaxial layer and a plurality of electrode unit on top; and performing a complex process, which removes the second metal layer on the lower surface of the first metal layer and part of the first metal layer and performs cutting according to the number of the electrode unit, so as to form a plurality of epitaxial die. Each epitaxial die corresponds to an electrode unit to form a magnetic light-emitting element. The proposed method improves soft magnetic properties of an original substrate and enables dies to reverse spontaneously, thereby used perfectly for industrial mass transfer technology.

Abstract: A light-emitting diode packaging structure and a method for fabricating the same is disclosed. A semiconductor wafer is provided, which includes semiconductor substrates. Each semiconductor substrate is penetrated with a first through hole and three second through holes. An insulation layer is formed on the surface of each semiconductor substrate and the inner surfaces of the first through hole, the first sub-through hole, and the second sub-through hole. A patterned electrode layer is formed on the top surface of the semiconductor substrate. A conductive material covering the insulation layer is formed in the first through hole and the second through hole and electrically connected to the patterned electrode layer. Three light-emitting diodes are respectively formed in the first sub-through holes of the second through holes of each semiconductor substrate and respectively electrically connected to the conductive material within the second through holes.

Abstract: A magnetic light-emitting structure and fabrication method for manufacturing a magnetic light-emitting element are provided. The fabrication method comprises providing a magnetic metal composite substrate, wherein a second metal layer is respectively disposed on an upper and lower surface of a first metal layer; forming a connecting metal layer, an epitaxial layer and a plurality of electrode unit on top; and performing a complex process, which removes the second metal layer on the lower surface of the first metal layer and part of the first metal layer and performs cutting according to the number of the electrode unit, so as to form a plurality of epitaxial die. Each epitaxial die corresponds to an electrode unit to form a magnetic light-emitting element. The proposed method improves soft magnetic properties of an original substrate and enables dies to reverse spontaneously, thereby used perfectly for industrial mass transfer technology.

Abstract: A magnetic light-emitting structure and fabrication method for manufacturing a magnetic light-emitting element are provided. The fabrication method comprises providing a magnetic metal composite substrate, wherein a second metal layer is respectively disposed on an upper and lower surface of a first metal layer; forming a connecting metal layer, an epitaxial layer and a plurality of electrode unit on top; and performing a complex process, which removes the second metal layer on the lower surface of the first metal layer and part of the first metal layer and performs cutting according to the number of the electrode unit, so as to form a plurality of epitaxial die. Each epitaxial die corresponds to an electrode unit to form a magnetic light-emitting element. The proposed method improves soft magnetic properties of an original substrate and enables dies to reverse spontaneously, thereby used perfectly for industrial mass transfer technology.

Abstract: A light-emitting diode packaging structure and a method for fabricating the same is disclosed. A semiconductor wafer is provided, which includes semiconductor substrates. Each semiconductor substrate is penetrated with a first through hole and three second through holes. An insulation layer is formed on the surface of each semiconductor substrate and the inner surfaces of the first through hole, the first sub-through hole, and the second sub-through hole. A patterned electrode layer is formed on the top surface of the semiconductor substrate. A conductive material covering the insulation layer is formed in the first through hole and the second through hole and electrically connected to the patterned electrode layer. Three light-emitting diodes are respectively formed in the first sub-through holes of the second through holes of each semiconductor substrate and respectively electrically connected to the conductive material within the second through holes.

Abstract: A magnetic light-emitting structure and fabrication method for manufacturing a magnetic light-emitting element are provided. The fabrication method comprises providing a magnetic metal composite substrate, wherein a second metal layer is respectively disposed on an upper and lower surface of a first metal layer; forming a connecting metal layer, an epitaxial layer and a plurality of electrode unit on top; and performing a complex process, which removes the second metal layer on the lower surface of the first metal layer and part of the first metal layer and performs cutting according to the number of the electrode unit, so as to form a plurality of epitaxial die. Each epitaxial die corresponds to an electrode unit to form a magnetic light-emitting element. The proposed method improves soft magnetic properties of an original substrate and enables dies to reverse spontaneously, thereby used perfectly for industrial mass transfer technology.

Abstract: An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.

Abstract: An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.

Abstract: A method for manufacturing micro light-emitting diode chips includes the steps of: providing a to-be-divided light-emitting component, which includes a metal substrate and a plurality of micro light-emitting diode dies disposed on the metal substrate to permit the metal substrate to define a to-be-etched region among the micro light-emitting diode dies; and etching the metal substrate to remove the to-be-etched region so as to divide the light-emitting component into a plurality of the micro light-emitting diode chips.

Abstract: A method for manufacturing micro light-emitting diode chips includes the steps of: providing a to-be-divided light-emitting component, which includes a metal substrate and a plurality of micro light-emitting diode dies disposed on the metal substrate to permit the metal substrate to define a to-be-etched region among the micro light-emitting diode dies; and etching the metal substrate to remove the to-be-etched region so as to divide the light-emitting component into a plurality of the micro light-emitting diode chips.

Abstract: The present technology relates generally to compositions and methods for creating recombinant T cell receptor (TCR) libraries and methods of their therapeutic use. The compositions and methods of the present technology are useful for rapid isolation of antigen-specific TCR repertoires as personalized, targeted therapies for cancer and viral infection.

Abstract: An operating method of low current electrically erasable programmable read only memory (EEPROM) array is provided. The EEPROM array comprises a plurality of bit line groups, word lines, common source lines, and sub-memory arrays. A first memory cell of each sub-memory array is connected with one bit line of a first bit line group, a first common source line, and a first word line. A second memory cell of each sub-memory array is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are symmetrically arranged at two opposite sides of the first common source line. By employing the proposed specific operation and bias conditions of the present invention, rapidly bytes programming and erasing functions with low current, low voltage and low cost goals are accomplished.

Abstract: The present invention discloses a method of fast erasing an EEPROM with low-voltages. The EEPROM includes a transistor structure is formed in a semiconductor substrate and the transistor structure includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for erasing. Moreover, the source or the drain is floated during erasing to achieve rapid erasing for a large number of memory cells. In addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.

Abstract: A method of fast erasing a low-current EEPROM array. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The source or the drain is floated during erasing to perform the fast bytes-erasing with low current, low voltage and low cost.

Abstract: A method for operating a low-current EEPROM array is disclosed. The EEPROM array comprises bit line groups, word lines, common source lines, and sub-memory arrays. Each sub-memory array includes a first memory cell and a second memory cell. The first memory cell is connected with one bit line of a first bit line group, a first common source line, and a first word line. The second memory cell is connected with the other bit line of the first bit line group, the first common source line, and a second word line. The first and second memory cells are operation memory cells and symmetrically arranged at two sides of the first common source line. The method uses special biases to perform the bytes writing and erasing with low current, low voltage and low cost.