Abstract: A metal-oxide-semiconductor device includes a substrate, a gate on the substrate, a source in the substrate and adjacent to one side of the gate, a drain in the substrate and adjacent to another side of the gate, a gate channel in the substrate and under the gate, and a gate insulator between the source and the drain and the gate and the gate channel, wherein the gate insulator has a substantially uneven thickness for use in electrostatic discharge (ESD) protection.

Abstract: An ESD protection device includes a substrate with a doped well of a first conductive type, a first and a second doping region of the first conductive type and a third and a fourth doping region of a second conductive type respectively disposed in the doped well, a first gate disposed on the substrate and between the first and the second doping region, and a second gate disposed on the substrate and between the second and the third doping region to determine the distance between the second and the third doping region in order to precisely adjust the breakdown voltage of the ESD protection device of the present invention.

Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Abstract: A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Abstract: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

Abstract: A MOS circuit arrangement includes a silicon substrate, a semiconductor device, a field oxide layer, and a poly-protective layer. The silicon substrate has a conductive doping incorporated therein, wherein the semiconductor device is electrically connected with the silicon substrate. The field oxide layer is formed on the silicon substrate at a position spaced apart from the terminal of the semiconductor device to form an active region between the field oxide layer and the semiconductor device. The poly-protective layer deposited on the active region to communicate the field oxide layer with the terminal of the semiconductor device, wherein the poly-protective layer provides a junction breakdown path between the semiconductor device and the silicon substrate to increase a junction breakdown voltage of the semiconductor device.

Abstract: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

Abstract: A semiconductor wafer includes a wafer body, a plurality of dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two the dies, wherein at least one of the dies is formed as a tested die having a terminal pad for measuring a voltage of the tested die via a measuring tool, and a test circuit having an output end and an input end electrically extended from an internal circuit of the tested die. An output impedance of the test circuit is relatively smaller than an impedance of the measuring tool, such that the voltage of the tested die adapted for being precisely measured when testing terminals of the measuring tool are electrically pointed at the tested die and the output end of the test circuit respectively.

Abstract: A semiconductor wafer includes a wafer body, a plurality of analog IC dies spacedly and alignedly formed on the wafer body to define a scribe line as a margin formed between each two dies wherein each of the dies has an internal circuit formed therewithin and at least a terminal pad formed along the scribe line, and a conductive arrangement including at least a conductive element formed on the wafer body to electrically connect the terminal pad with the internal circuit of the die in such a manner that when the die is cut off from the wafer body along the scribe line, the terminal pad is cut off from the die so as to keep the internal circuit in the die.

Abstract: A method for transferring patterns. After a patterned photoresist is formed on a substrate, the patterned photoresist is hardened, and the pattern of the hardened patterned photoresist is transferred into the substrate. Moreover, a popular method to harden is the silylation process, it is acceptable to only harder the top of the patterned photoresist or to harden both the top and the sidewall of the patterned photoresist. Besides, it is optional to change the thickness and the critical dimension of the patterned photoresist before it is hardened. Significantly, because the etch resistance of hardened patterned photoresist is higher than that of the non-hardened patterned photoresist, the method can improve any defect induced by etched photoresist during the pattern transferring process. Similarly, because a thinner non-hardened photoresist is available for the method, a smaller critical dimension of the patterned photoresist is available for the method while the photolithography technology being not improved.

Abstract: A method of spin-on-glass planarization. A spin-on-glass layer is formed on a substrate. An accuflo layer with a better fluidity than the spin-on-glass material is formed on the spin-on-glass layer. The accuflo layer and the spin-on-glass layer are etched back by two etching steps with different etching rate. The accuflo layer after being etched is stripped. A dielectric layer is formed.

Abstract: A method of forming an inter-metal dielectric layer using hydrogen silsesquoxane (HSQ) as one of the dielectric layers. HSQ is a highly fluidic material that has a high gap-filling capacity. Therefore, the desired thickness and uniformity can be obtained in a single coating operation. Furthermore, when the HSQ layer is cured in an atmosphere of gaseous nitrogen, the HSQ layer is able to attain a high degree of planarity. Consequently, there is no need to planarize the dielectric layer before carrying out subsequent operations.