Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.

Abstract: A server includes a relay unit adapted to transmit a video data related to a livestream from a terminal of a livestreamer of the livestream to a terminal of a viewer, a determination unit adapted to determine whether the livestream has been terminated for an unexpected reason, a maintaining unit adapted to maintain a state of the livestream when it is determined that the livestream has been terminated, and a resume unit adapted to resume the livestream with the maintained state when the resume unit receives an instruction to resume the livestream from the terminal of the livestreamer within a predetermined period after it is determined that the livestream has been terminated.

Abstract: A network device includes a processor circuit and transceiver circuits. The transceiver circuits are connected to a wireless access point via a base channel based on a control of the processor circuit. The wireless access point is connected to a first device. The processor circuit determines whether a tunneled direct link setup link (TDLS) throughput of the base channel is higher than or equal to a threshold value; if the TDLS throughput is higher than or equal to the threshold value, performs an auto channel selection algorithm to determine whether to establish an off channel; and if the off channel is established, performs one of a dual-band concurrent mode and a multi-channel concurrent mode according to a number of antennas corresponding to the transceiver circuits, in order to control at least one of the transceiver circuits to be connected to the first device via the off channel.

Abstract: An inverter includes an inverter case, a plurality of power modules and a plurality of cooling fins. The inverter case includes an annular portion, a supporting portion and a cooling liquid flow channel. The cooling liquid flow channel is a sealed channel located in the annular portion and the supporting portion, and a cooling liquid inlet and an inverter case cooling liquid flow channel outlet are formed on the annular portion at two ends of the cooling liquid flow channel. The power module is arranged on the supporting portion, and the cooling fins are arranged on the cooling liquid flow channel, the fin parts of the cooling fins are respectively extended and arranged inside the cooling liquid flow channel, and the contact parts of the cooling fins are respectively extended to contact heat transfer parts of corresponding power modules.

Abstract: A device includes a semiconductor substrate, a fin structure on the semiconductor substrate, a gate structure on the fin structure, and a pair of source/drain features on both sides of the gate structure. The gate structure includes an interfacial layer on the fin structure, a gate dielectric layer on the interfacial layer, and a gate electrode layer of a conductive material on and directly contacting the gate dielectric layer. The gate dielectric layer includes nitrogen element.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.

Abstract: The present disclosure, in some embodiments, relates to an image sensor integrated chip. The image sensor integrated chip includes a substrate having a first side and a second side opposing the first side. The substrate has one or more sidewalls defining a trench extending along opposing sides of a pixel region having a first width. An isolation structure including one or more dielectric materials is disposed within the trench. The isolation structure has a second width. An image sensing element and a focal region are disposed within the pixel region. The focal region is configured to receive incident radiation along the second side of the substrate. A ratio of the second width to the first width is in a range of between approximately 0.1 and approximately 0.2, so that the focal region is completely confined between interior sidewall of the isolation structure facing the image sensing element.

Abstract: An encoder may be configured to receive a first input from a user. The encoder may include a first user input area. A configurator may be configured to communicate with the encoder and the encoder may be configured to communicate with a CPU. The encoder may receive the first input from the user at the first user input area based on an encoder configuration defined by the configurator. The encoder may communicate the first input to the CPU based on the encoder configuration defined by the configurator. A panel may be configured to receive a first input from a user. The panel may include a plurality of input areas. A portable computing device may comprise a configurator. The portable computing device may be configured to communicate with a CPU.

Abstract: An encoder may be configured to receive a first input from a user. The encoder may include a first user input area. A configurator may be configured to communicate with the encoder and the encoder may be configured to communicate with a CPU. The encoder may receive the first input from the user at the first user input area based on an encoder configuration defined by the configurator. The encoder may communicate the first input to the CPU based on the encoder configuration defined by the configurator. A panel may be configured to receive a first input from a user. The panel may include a plurality of input areas. A portable computing device may comprise a configurator. The portable computing device may be configured to communicate with a CPU.

Abstract: An encoder may be configured to receive a first input from a user. The encoder may include a first user input area. A configurator may be configured to communicate with the encoder and the encoder may be configured to communicate with a CPU. The encoder may receive the first input from the user at the first user input area based on an encoder configuration defined by the configurator. The encoder may communicate the first input to the CPU based on the encoder configuration defined by the configurator. A panel may be configured to receive a first input from a user. The panel may include a plurality of input areas. A portable computing device may comprise a configurator. The portable computing device may be configured to communicate with a CPU.

Abstract: An interactive image processing system including a first infrared camera, a second infrared camera, an image processing circuit, a vision processing unit, an image signal processor, a central processing unit, and a memory device is disclosed. The present disclosure calculates depth data according to infrared images generated by the first and second infrared cameras to improve depth quality.

Abstract: An encoder may be configured to receive a first input from a user. The encoder may include a first user input area. A configurator may be configured to communicate with the encoder and the encoder may be configured to communicate with a CPU. The encoder may receive the first input from the user at the first user input area based on an encoder configuration defined by the configurator. The encoder may communicate the first input to the CPU based on the encoder configuration defined by the configurator. A panel may be configured to receive a first input from a user. The panel may include a plurality of input areas. A portable computing device may comprise a configurator. The portable computing device may be configured to communicate with a CPU.

Abstract: An apparatus for interactive image processing including a first camera, a second camera, an image processing circuit, a vision processing unit, an image signal processor, a central processing unit, and a memory device is disclosed. The present disclosure utilizes the image processing circuit to calculate depth data according to raw images generated by the first and second cameras at the front-end of the interactive image processing system, so as to ease the burden of depth calculation by the digital signal processor in the prior art.

Abstract: A system and a method for processing images related to depth are provided. In the method, a first image sensor generates a first image. A second image sensor generates a second image. A first image processing circuit generates depth data corresponding to one or more objects identified in the first and the second image. The first image processing circuit generates a first data packet including two of the first image, the second image, and the depth data. A second image processing circuit receives the first data packet. The second image processing circuit performs stereo matching on the first image and the second image. Therefore, the efficiency of processing data could be improved.

Abstract: An interactive image processing system including a first infrared camera, a second infrared camera, an image processing circuit, a vision processing unit, an image signal processor, a central processing unit, and a memory device is disclosed. The present disclosure calculates depth data according to infrared images generated by the first and second infrared cameras to improve depth quality.

Abstract: An apparatus for interactive image processing including a first camera, a second camera, an image processing circuit, a vision processing unit, an image signal processor, a central processing unit, and a memory device is disclosed. The present disclosure utilizes the image processing circuit to calculate depth data according to raw images generated by the first and second cameras at the front-end of the interactive image processing system, so as to ease the burden of depth calculation by the digital signal processor in the prior art.

Abstract: An apparatus for interactive image processing including a first camera, a second camera, an image processing circuit, a vision processing unit, an image signal processor, a central processing unit, and a memory device is disclosed. The present disclosure utilizes the image processing circuit to calculate depth data according to raw images generated by the first and second cameras at the front-end of the interactive image processing system, so as to ease the burden of depth calculation by the digital signal processor in the prior art.

Abstract: An encoder may be configured to receive a first input from a user. The encoder may include a first user input area. A configurator may be configured to communicate with the encoder and the encoder may be configured to communicate with a CPU. The encoder may receive the first input from the user at the first user input area based on an encoder configuration defined by the configurator. The encoder may communicate the first input to the CPU based on the encoder configuration defined by the configurator. A panel may be configured to receive a first input from a user. The panel may include a plurality of input areas. A portable computing device may comprise a configurator. The portable computing device may be configured to communicate with a CPU.

Abstract: An encoder may be configured to receive a first input from a user. The encoder may include a first user input area. A configurator may be configured to communicate with the encoder and the encoder may be configured to communicate with a CPU. The encoder may receive the first input from the user at the first user input area based on an encoder configuration defined by the configurator. The encoder may communicate the first input to the CPU based on the encoder configuration defined by the configurator. A panel may be configured to receive a first input from a user. The panel may include a plurality of input areas. A portable computing device may comprise a configurator. The portable computing device may be configured to communicate with a CPU.