Abstract: A method of performing automatic tuning on a deep learning model includes: utilizing an instruction-based learned cost model to estimate a first type of operational performance metrics based on a tuned configuration of layer fusion and tensor tiling; utilizing statistical data gathered during a compilation process of the deep learning model to determine a second type of operational performance metrics based on the tuned configuration of layer fusion and tensor tiling; performing an auto-tuning process to obtain a plurality of optimal configurations based on the first type of operational performance metrics and the second type of operational performance metrics; and configure the deep learning model according to one of the plurality of optimal configurations.

Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.

Abstract: An electronic device is provided. The electronic device includes an antenna array including a plurality of antenna patterns collectively configured to provide a scan-angle coverage. Each of the antenna patterns includes a curved surface.

Abstract: A device includes one or more processors configured to perform signal processing including a linear transformation and a non-linear transformation of an input signal to generate a reference target signal. The reference target signal has a linear component associated with the linear transformation and a non-linear component associated with the non-linear transformation. The one or more processors are also configured to perform linear filtering of the input signal by controlling adaptation of the linear filtering to generate an output signal that substantially matches the linear component of the reference target signal.

Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.

Abstract: A device includes one or more processors configured to perform signal processing including a linear transformation and a non-linear transformation of an input signal to generate a reference target signal. The reference target signal has a linear component associated with the linear transformation and a non-linear component associated with the non-linear transformation. The one or more processors are also configured to perform linear filtering of the input signal by controlling adaptation of the linear filtering to generate an output signal that substantially matches the linear component of the reference target signal.

Abstract: Methods, systems, computer-readable media, and apparatuses for signal enhancement are presented. One example of such an apparatus includes a receiver configured to produce a remote speech signal from information carried by a wireless signal; a signal canceller configured to perform a signal cancellation operation on a local speech signal to generate a room response; and a filter configured to filter the remote speech signal according to the room response to produce a filtered speech signal. In this example, the signal cancellation operation is based on the remote speech signal as a reference signal.

Abstract: A semiconductor device includes a semiconductor substrate, a capacitor, and an interconnection layer. The capacitor is over the semiconductor substrate and includes a bottom electrode, a top electrode, and an insulator layer. The top electrode has a top surface and a bottom surface rougher than the top surface of the top electrode. The insulator layer is between the bottom electrode and the top electrode. The interconnection layer is over the semiconductor substrate and is electrically connected to the capacitor.

Abstract: Methods, systems, computer-readable media, and apparatuses for signal enhancement are presented. One example of such an apparatus includes a receiver configured to produce a remote speech signal from information carried by a wireless signal; a signal canceller configured to perform a signal cancellation operation on a local speech signal to generate a room response; and a filter configured to filter the remote speech signal according to the room response to produce a filtered speech signal. In this example, the signal cancellation operation is based on the remote speech signal as a reference signal.

Abstract: Methods, systems, computer-readable media, and apparatuses for gesture control are presented. One example includes indicating, based on information from a first audio input signal, a presence of an object in proximity to a microphone, and increasing a volume level in response to the indicating.

Abstract: An electronic apparatus and a display backlight control method are provided. The electronic apparatus includes a display, a processing unit, a read-only memory and a backlight controller. The read-only memory stores a basic input output system (BIOS) and a setting table. The setting table includes a plurality of backlight setting values corresponding to each of the displays. When the processing unit executes the BIOS, the processing unit identifies an identifier corresponding to the display connected to the electronic apparatus, so as to obtain the backlight setting values corresponding to the display according to the identifier and the setting table. Then the processing unit provides the backlight setting values to the backlight controller, and the backlight controller controls the backlight power of the display according to the backlight setting values.

Abstract: An electronic apparatus and a display backlight control method are provided. The electronic apparatus includes a display, a processing unit, a read-only memory and a backlight controller. The read-only memory stores a basic input output system (BIOS) and a setting table. The setting table includes a plurality of backlight setting values corresponding to each of the displays. When the processing unit executes the BIOS, the processing unit identifies an identifier corresponding to the display connected to the electronic apparatus, so as to obtain the backlight setting values corresponding to the display according to the identifier and the setting table. Then the processing unit provides the backlight setting values to the backlight controller, and the backlight controller controls the backlight power of the display according to the backlight setting values.

Abstract: The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxN1?x/TaN/TaxN1?x/Ta (tantalum/tantalumx nitride1?x/tantalum nitride/tantalumx nitride1?x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1?x films. After subsequent thermal cycle processes such as metal alloy, the inter-layer diffusion occurs and a more smooth distribution of Ta and N is achieved for the gradient barrier.

Abstract: The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxN1−x/TaN/TaxN1−x/Ta (tantalum/tantalumx nitride1−x/tantalum nitride/tantalumx nitride1−x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1−x films.

Abstract: The present invention is directed to a structure of a gradient barrier layer. The gradient barrier with a composite structure of metal/metal salt of different composition/metal such as Ta/TaxNl−x/TaN/TaxNl−x/Ta (tantalum/tantalumx nitride1−x/tantalum nitride/tantalumx nitride1−x/tantalum) is proposed to replace the conventional barrier for copper metallization. The gradient barrier can be formed in a chemical vapor deposition (CVD) process or a multi-target physical vapor deposition (PVD) process. For CVD process, using the characteristics of well-controlled reaction gas injection, the ratio of tantalum (Ta) and nitrogen (N) can be modulated gradually to form the gradient barrier. For the multi-target PVD process, the gradient barrier is formed by depositing multi-layers of different composition TaxN1−x films.

Abstract: A metal interconnect structure generally includes a lower-layer metal wiring, an upper-layer metal wiring partially overlapping with the lower-layer metal wiring to define a via region thereof, a dielectric layer disposed between the lower-layer metal wiring and the upper-layer metal wiring, a plurality of via plugs arranged in the dielectric layer within a first area of the via region for electrically connecting the lower-layer metal wiring and the upper-layer metal wiring, and a plurality of first dielectric structures embedded in the upper-layer metal wiring within a second area of the via region, in which the first area does not overlap with the second area.

Abstract: A bonding pad structure for copper/low-k dielectric material back end of the line (BEOL) processes is disclosed. The bonding pad structure uses a dielectric layer and a conductive pad formed by a gap fill process to protect the underlying bonding pad structure. The conductive pad has a plurality of via plugs in the dielectric layer connecting the underlying bonding pad structure. The bonding pad structure also has a passivation layer having a pad window with a smooth contour to expose the conductive pad.

Abstract: A gate structure is patterned on a substrate. An ion implantation is performed to form the LDD. Then, a thin liner layer is deposited on the feature of the substrate. A disposable spacer is successively formed attached on the side of the linear layer. The source and drain is next created in the substrate by ion implantation. The disposable spacer is then stripped by wet dip technique. A borderless layer is formed on the surface of the linear layer. A dielectric layer is formed on the gate structure and the dielectric layer can be composed of silicon dioxide, BPSG, SOG. Then, a photoresist is patterned on the dielectric layer to define the contact hole.