Patents by Inventor CHENG-YU KUO
CHENG-YU KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250147245Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a photonic integrated circuit component, an electric integrated circuit component, a lens and an optical signal port. The photonic integrated circuit component comprises an optical input/output portion configured to transmit and receive optical signal. The electric integrated circuit component is electrically connected to the photonic integrated circuit component. The lens is disposed on a sidewall of the photonic integrated circuit component. The optical signal port is optically coupled to the optical input/output portion.Type: ApplicationFiled: November 7, 2023Publication date: May 8, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Chih Lin, Hsuan-Ting Kuo, Cheng-Yu Kuo, Yen-Hung Chen, Chia-Shen Cheng, Chao-Wei Li, Ching-Hua Hsieh, Wen-Chih Chiou
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Publication number: 20250093593Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.Type: ApplicationFiled: January 3, 2024Publication date: March 20, 2025Inventors: Wen-Chih Lin, Cheng-Yu Kuo, Yen-Hung Chen, Hsuan-Ting Kuo, Chia-Shen Cheng, Chao-Wei Li, Ching-Hua Hsieh, Wen-Chih Chiou, Ming-Fa Chen, Shang-Yun Hou
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Publication number: 20240387150Abstract: An edge assembly used for a plasma etching system is provided. The edge assembly includes: a focus ring peripherally surrounding an edge portion of a mounting platform mounted in the plasma etching system. The focus ring includes: a lower step portion proximate to the edge portion, the lower step portion extending vertically from a bottom surface of the focus ring to a lower step top surface; and an upper step portion distal to the edge portion, the upper step portion extending vertically from the bottom surface of the focus ring to an upper step top surface and extending radially from an upper step inner side to an upper step outer side. The focus ring is characterized by an air gap located in the upper step portion, and the air gap extends peripherally along a circumstance of the focus ring.Type: ApplicationFiled: May 19, 2023Publication date: November 21, 2024Inventors: Chia-Wei Chen, Chao Yi Chan, Yo-Xuan Chen, Cheng-Yu Kuo, Yen-Yu Chen
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Publication number: 20240274440Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: ApplicationFiled: April 10, 2024Publication date: August 15, 2024Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
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Publication number: 20240198651Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.Type: ApplicationFiled: February 29, 2024Publication date: June 20, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Patent number: 11993066Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.Type: GrantFiled: August 5, 2021Date of Patent: May 28, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Patent number: 11984323Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: GrantFiled: July 12, 2021Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
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Publication number: 20240063048Abstract: A workpiece chuck includes a supporting platform, a vacuum system, and a gas permeable buffer layer. The supporting platform has a supporting surface for holding a workpiece thereon. The vacuum system is disposed under and in gas communication with the supporting platform. The gas permeable buffer layer is disposed over the supporting platform and covers the supporting surface, wherein a hardness scale of the gas permeable buffer layer is smaller than a hardness scale of the supporting platform.Type: ApplicationFiled: August 16, 2022Publication date: February 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ching Lo, Ching-Pin Yuan, Wei-Jie Huang, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Publication number: 20240017538Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.Type: ApplicationFiled: August 2, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Publication number: 20230307404Abstract: A package structure includes a die, a first redistribution circuit structure, a first redistribution circuit structure, a second redistribution circuit structure, an enhancement layer, first conductive terminals, and second conductive terminals. The first redistribution circuit structure is disposed on a rear side of the die and electrically coupled to thereto. The second redistribution circuit structure is disposed on an active side of the die and electrically coupled thereto. The enhancement layer is disposed on the first redistribution circuit structure. The first redistribution circuit structure is disposed between the enhancement layer and the die. The first conductive terminals are connected to the first redistribution circuit structure. The first redistribution circuit structure is between the first conductive terminals and the die. The second conductive terminals are connected to the second redistribution circuit structure.Type: ApplicationFiled: March 28, 2022Publication date: September 28, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Yu-Ching Lo, Wei-Jie Huang, Ching-Pin Yuan, Yi-Che Chiang, Kris Lipu Chuang, Hsin-Yu Pan, Yi-Yang Lei, Ching-Hua Hsieh, Kuei-Wei Huang
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Publication number: 20230115449Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: ApplicationFiled: December 13, 2022Publication date: April 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Patent number: 11569183Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: GrantFiled: December 14, 2020Date of Patent: January 31, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Publication number: 20220314595Abstract: A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.Type: ApplicationFiled: August 5, 2021Publication date: October 6, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Jie Huang, Yu-Ching Lo, Ching-Pin Yuan, Wen-Chih Lin, Cheng-Yu Kuo, Yi-Yang Lei, Ching-Hua Hsieh
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Publication number: 20210343538Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: ApplicationFiled: July 12, 2021Publication date: November 4, 2021Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
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Patent number: 11069652Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.Type: GrantFiled: January 14, 2020Date of Patent: July 20, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Alexander Kalnitsky, Yi-Yang Lei, Hsi-Ching Wang, Cheng-Yu Kuo, Tsung Lung Huang, Ching-Hua Hsieh, Chung-Shi Liu, Chen-Hua Yu, Chin-Yu Ku, De-Dui Liao, Kuo-Chio Liu, Kai-Di Wu, Kuo-Pin Chang, Sheng-Pin Yang, Isaac Huang
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Patent number: 11069533Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: GrantFiled: July 18, 2019Date of Patent: July 20, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
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Publication number: 20210098395Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Publication number: 20210020449Abstract: A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.Type: ApplicationFiled: July 18, 2019Publication date: January 21, 2021Inventors: Te-Chien Hou, Yu-Ting Yen, Cheng-Yu Kuo, Chih Hung Chen, William Weilun Hong, Kei-Wei Chen
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Patent number: 10867939Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: GrantFiled: June 14, 2019Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang
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Publication number: 20200168568Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.Type: ApplicationFiled: June 14, 2019Publication date: May 28, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yu Kuo, Ching-Hua Hsieh, Chen-Hua Yu, Chung-Shi Liu, Yi-Yang Lei, Wei-Jie Huang