Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a first source/drain feature and a second source/drain feature, a plurality of semiconductor layers vertically stacked and disposed between the first and second source/drain features, a gate electrode layer surrounding a portion of each of the plurality of the semiconductor layers, and an interfacial layer (IL) disposed between the gate electrode layer and one of the plurality of the semiconductor layers, wherein a topmost semiconductor layer of the plurality of the semiconductor layers has a first length, and the IL has a second length greater than the first length.

Abstract: A method for establishing a 3D medical imaging model of a subject is to be implemented by an X-ray computed tomography (CT) scanner and a processor. The method includes: emitting X-rays on the subject sequentially from plural angles with respect to the subject to obtain M number of X-ray images of the subject in sequence; obtaining, for each pair of consecutive X-ray images, K number of intermediate image(s) by using the pair of consecutive X-ray images as inputs to a convolutional neural network (CNN) model that has been trained for frame interpolation; and establishing the 3D medical imaging model by using a 3D reconstruction technique based on the M number of X-ray images and the intermediate images obtained for the M number of X-ray images.

Abstract: A method for establishing a 3D medical imaging model of a subject is to be implemented by an X-ray computed tomography (CT) scanner and a processor. The method includes: emitting X-rays on the subject sequentially from plural angles with respect to the subject to obtain M number of X-ray images of the subject in sequence; obtaining, for each pair of consecutive X-ray images, K number of intermediate image(s) by using the pair of consecutive X-ray images as inputs to a convolutional neural network (CNN) model that has been trained for frame interpolation; and establishing the 3D medical imaging model by using a 3D reconstruction technique based on the M number of X-ray images and the intermediate images obtained for the M number of X-ray images.

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract: A semiconductor device with oxygen-containing metal gates includes a substrate, a gate dielectric layer and a multi-layered stack structure. The multi-layered stack structure is disposed on the substrate. At least one layer of the multi-layered stack structure includes a work function metal layer. The concentration of oxygen in the side of one layer of the multi-layered stack structure closer to the gate dielectric layer is less than that in the side of one layer of the multi-layered stack structure opposite to the gate dielectric layer.

Abstract: A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the source layer is removed and a metal layer fills up the gate trench.

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

Abstract: A method for fabricating a metal gate includes the following steps. First, a substrate having an interfacial dielectric layer above the substrate is provided. Then, a gate trench having a barrier layer is formed in the interfacial dielectric layer. A source layer is disposed above the barrier layer. Next, a process is performed to have at least one element in the source layer move into the barrier layer. Finally, the barrier layer is removed and a metal layer fills up the gate trench.

Abstract: A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An O2 ambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Abstract: A method for forming a transistor having a metal gate is provided. A substrate is provided first. A transistor is formed on the substrate. The transistor includes a high-k gate dielectric layer, an oxygen containing dielectric layer disposed on the high-k gate dielectric layer, and a dummy gate disposed on the oxygen containing dielectric layer. Then, the dummy gate and the patterned gate dielectric layer are removed. Lastly, a metal gate is formed and the metal gate directly contacts the high-k gate oxide.

Abstract: A method for fabricating metal gate transistor is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a transistor region defined thereon; forming a gate insulating layer on the substrate; forming a stacked film on the gate insulating layer, wherein the stacked film comprises at least one etching stop layer, a polysilicon layer, and a hard mask; patterning the gate insulating layer and the stacked film for forming a dummy gate on the substrate; forming a dielectric layer on the dummy gate; performing a planarizing process for partially removing the dielectric layer until reaching the top of the dummy gate; removing the polysilicon layer of the dummy gate; removing the etching stop layer of the dummy gate for forming an opening; and forming a conductive layer in the opening for forming a gate.

Abstract: A method for sensing and analyzing data with surface acoustic wave (SAW) devices comprises the steps of: propagating a sampling signal at a fundamental frequency through a SAW device coated for selective adsorption; measuring at least one parameter of at least one higher order harmonic of the fundamental frequency sampling signal; exposing the coated SAW device to enable the selective adsorption; measuring the at least one parameter of the at least one higher order harmonic of the fundamental frequency sampling signal after the exposing step; comparing the measurements of the at least one parameter of the at least one higher order harmonic before and after the exposing step; and, deriving a result of the selective adsorption based upon the comparing step. The at least one parameter is harmonic power and harmonic frequency. The at least one higher order harmonic is one or more odd harmonics.