Patents by Inventor Cheng-Yuan Chen

Cheng-Yuan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088001
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 14, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin HO, Chih-Cheng LEE, Chun Chen CHEN, Cheng Yuan CHEN
  • Publication number: 20230298985
    Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S 11 parameter of the connector is less than ?20 dB.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Cheng Yuan CHEN, Chun Chen CHEN, Jiming LI, Chien-Wen TU
  • Patent number: 11764137
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: September 19, 2023
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Cheng Yuan Chen
  • Patent number: 11658102
    Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than ?20 dB.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: May 23, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yuanhao Yu, Cheng Yuan Chen, Chun Chen Chen, Jiming Li, Chien-Wen Tu
  • Publication number: 20230145588
    Abstract: A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 11, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng Yuan CHEN, Jiming LI, Chun Chen CHEN, Yuanhao YU
  • Patent number: 11552026
    Abstract: A semiconductor package includes a substrate, a preformed feeding element, a preformed shielding element, and an encapsulant. The preformed feeding element is disposed on the substrate and the preformed feeding element is disposed on the substrate and adjacent to the preformed feeding element. The encapsulant encapsulates the preformed feeding element and the preformed shielding element.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 10, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng Yuan Chen, Jiming Li, Chun Chen Chen, Yuanhao Yu
  • Patent number: 11133245
    Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 28, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Tsung Chiu, Hui-Ying Hsieh, Kuo-Hua Chen, Cheng Yuan Chen
  • Patent number: 11127707
    Abstract: A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 21, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Tsung Chiu, Hui-Ying Hsieh, Hui Hua Lee, Cheng Yuan Chen
  • Publication number: 20210225747
    Abstract: A semiconductor device package includes a carrier, an electronic component and a connector. The electronic component is disposed on the carrier. The connector is disposed on the carrier and electrically connected to the electronic component. A S11 parameter of the connector is less than ?20 dB.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 22, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yuanhao YU, Cheng Yuan CHEN, Chun Chen CHEN, Jiming LI, Chien-Wen TU
  • Publication number: 20210125911
    Abstract: A semiconductor package structure includes a base, at least one semiconductor element, a first dielectric layer, a second dielectric layer and a circuit layer. The semiconductor element is disposed on the base and has an upper surface. The first dielectric layer covers at least a portion of a peripheral surface of the semiconductor element and has a top surface. The top surface is non-coplanar with the upper surface of the semiconductor element. The second dielectric layer covers the semiconductor element and the first dielectric layer. The circuit layer extends through the second dielectric layer to electrically connect the semiconductor element.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 29, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Tsung CHIU, Hui-Ying HSIEH, Kuo-Hua CHEN, Cheng Yuan CHEN
  • Publication number: 20210020594
    Abstract: A semiconductor package structure includes a base material, at least one semiconductor chip, an encapsulant, a depression structure, a redistribution layer and at least one conductive via. The semiconductor chip is disposed on the base material. The encapsulant is disposed on the base material and covers the at least one semiconductor chip. The encapsulant has an outer side surface. The depression structure is disposed adjacent to and exposed from of the outer side surface the encapsulant. The redistribution layer is disposed on the encapsulant. The conductive via is disposed in the encapsulant and electrically connects the semiconductor chip and the redistribution layer.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Tsung CHIU, Hui-Ying HSIEH, Hui Hua LEE, Cheng Yuan CHEN
  • Patent number: 10341522
    Abstract: An image capture and output method comprises steps of providing an image capture device, continuously capturing a plurality of line images from an initial position and recording a position information corresponded to each line image, calculating the difference between the position information of the first line image and the initial position and the differences between the position information of each of the rest line images and a former one of the line image to obtain a fill information, filling each line image into an image buffer according to the fill information, and outputting the image buffer as a product image. Therefore, the deformation issue is effectively solved, the storage memory is saved, and the manufacturing cost is lowered.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: July 2, 2019
    Assignee: TECO IMAGE SYSTEMS CO., LTD.
    Inventors: Nai-Wun Luo, Cheng-Yuan Chen
  • Publication number: 20190158694
    Abstract: An image capture and output method comprises steps of providing an image capture device, continuously capturing a plurality of line images from an initial position and recording a position information corresponded to each line image, calculating the difference between the position information of the first line image and the initial position and the differences between the position information of each of the rest line images and a former one of the line image to obtain a fill information, filling each line image into an image buffer according to the fill information, and outputting the image buffer as a product image. Therefore, the deformation issue is effectively solved, the storage memory is saved, and the manufacturing cost is lowered.
    Type: Application
    Filed: December 15, 2017
    Publication date: May 23, 2019
    Inventors: Nai-Wun Luo, Cheng-Yuan Chen
  • Publication number: 20170221345
    Abstract: A smart helmet system includes a helmet and a mobile communication device. The smart helmet includes a helmet body, a detection module and a wireless transmission module. The detection module is applied to detect at least one motion parameter of the helmet. The wireless transmission module is to transmit the motion parameter. The mobile communication device stores an operation regulation to define at least one predetermined operation function of the mobile communication device corresponding to at least one set motion track. The mobile communication device is to receive the motion parameter to accordingly determine a detected motion track and further to activate the predetermined operation function when the detected motion track is complied with the set motion track, so as to operate the mobile communication device according to the predetermined operation function.
    Type: Application
    Filed: March 21, 2016
    Publication date: August 3, 2017
    Inventor: Cheng-Yuan CHEN
  • Patent number: 8768000
    Abstract: An improved structure for an amplifier comprises: a single member, which at least has a frame, an edge and a membrane; and a positioning shrapnel, which is assembled by an inner frame, an outer frame and a plurality of flexible braces, the outer frame is firmly disposed at the frame of the single member, the plurality of flexible braces is disposed between the inner frame and the outer frame, the inner frame is firmly disposed on the membrane of the single member, wherein the peripheral of the frame has a fillister that can be embedded in by the outer frame, each connection of any of the flexible braces and the inner frame is a curve portion that is to keep the connection of the inner frame and the outer frame while a height difference is existed between the inner frame and the outer frame.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: July 1, 2014
    Assignee: Global Target Enterprise Inc.
    Inventors: Cheng-Yuan Chen, Hong-Bing Tsai
  • Publication number: 20120183157
    Abstract: An improved structure for an amplifier comprises: a single member, which at least has a frame, an edge and a membrane; and a positioning shrapnel, which is assembled by an inner frame, an outer frame and a plurality of flexible braces, the outer frame is firmly disposed at the frame of the single member, the plurality of flexible braces is disposed between the inner frame and the outer frame, the inner frame is firmly disposed on the membrane of the single member, wherein the peripheral of the frame has a fillister that can be embedded in by the outer frame, each connection of any of the flexible braces and the inner frame is a curve portion that is to keep the connection of the inner frame and the outer frame while a height difference is existed between the inner frame and the outer frame.
    Type: Application
    Filed: April 18, 2011
    Publication date: July 19, 2012
    Inventors: Cheng-Yuan Chen, Hong-Bing Tsai
  • Publication number: 20110128595
    Abstract: A scanning speed adjusting method is used in a scanning system including a scanning module and a controller. Firstly, a document is scanned by the scanning module, thereby generating an image data. Then, the image data is received by the controller, and transmitted to an output device. An input speed of receiving the image data from the scanning module and an output speed of transmitting the image data to the output device are detected by the controller. If the input speed and the output speed are different, a scanning speed of the scanning module is adaptively adjusted according to a difference between the input speed and the output speed.
    Type: Application
    Filed: July 2, 2010
    Publication date: June 2, 2011
    Inventor: Cheng-Yuan Chen
  • Publication number: 20090168080
    Abstract: A method of poster printing control, applicable to a multi-functional printer, comprising at least one printing module and a scanning module, includes using a scanning module to scan an original paper to obtain a digital copy of known size; setting a size of a paper to be printed; dividing the digital copy into a plurality of sub-images; up-scaling the sub-images to the size of the paper to be printed; using the printing module to print out the sub-images on the paper to be printed. Thereby, the poster printing is completed by means of the multi-functional printer.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 2, 2009
    Inventors: Cheng-Yuan Chen, Jui-Yang Huang, Lin-Ying Huang
  • Patent number: 7061412
    Abstract: An apparatus, method and digital-to-analog converter (DAC) for reducing harmonic error power is provided, suitable for current-mode self-calibration DAC. Unit currents are calibrated one by one based on a reference value and the error distribution of the unit currents appears identical characteristic. According to the calibrated current error distribution, a shift shifts the input digital signal so that the error distribution of the unit current selected by the digital signal is monotonicity and not related to self-calibration current period. A coarse decoder decodes the digital signal as compensation decoding. The harmonic power related to the self-calibration current period is greatly reduced, which improves the signal to noise ratio.
    Type: Grant
    Filed: July 5, 2005
    Date of Patent: June 13, 2006
    Assignee: Sunplus Technology Co., Ltd.
    Inventors: Shiao-Feng Wang, Cheng-Yuan Chen
  • Patent number: 6174793
    Abstract: A method for enhancing adhesion ability between copper and silicon nitride is disclosed. The present method comprises following steps: first, provide a substrate and then form a copper layer on the substrate; second, form a copper phosphide layer on the copper layer; and finally, form a silicon nitride layer on the copper phosphide layer. Herein, the copper phosphide layer is formed by a plasma enhanced chemical vapor deposition process. Therefore, any copper oxide layer that covers copper layer is replaced by the silicon phosphide layer and then adhesion between copper and silicon nitride is improved. Moreover, the silicon phosphide comprises two advantages: low resistance than copper oxide and efficiently prevent copper diffuses into surrounding dielectric layer.
    Type: Grant
    Filed: October 11, 1999
    Date of Patent: January 16, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Yuan-Chen Tsai, Chih-Chien Liu, Juan-Yuan Wu