Patents by Inventor Cheng-Yuan HSIEH
Cheng-Yuan HSIEH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11989005Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: GrantFiled: September 30, 2021Date of Patent: May 21, 2024Assignee: MediaTek Inc.Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Publication number: 20240161660Abstract: A display device and a housing of the display device are provided. The housing of the display device includes a reflective cover. The reflective cover has a plurality of segments formed on a front side of the reflective cover and a plurality of segment structures correspondingly formed on a rear side of the reflective cover. At least one of the segment structures has a notch formed thereat. Positions of the notches of the at least two adjacent ones of the segment structures are not opposite to each other.Type: ApplicationFiled: November 15, 2023Publication date: May 16, 2024Inventors: CHENG-YAN HSIEH, SHIH-YUAN KUO, Jie-Ting Tsai
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Patent number: 11953740Abstract: A package structure including a photonic, an electronic die, an encapsulant and a waveguide is provided. The photonic die includes an optical coupler. The electronic die is electrically coupled to the photonic die. The encapsulant laterally encapsulates the photonic die and the electronic die. The waveguide is disposed over the encapsulant and includes an upper surface facing away from the encapsulant. The waveguide includes a first end portion and a second end portion, the first end portion is optically coupled to the optical coupler, and the second end portion has a groove on the upper surface.Type: GrantFiled: May 14, 2021Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
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Patent number: 11947173Abstract: A package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler; an interconnect structure over the photonic layer; an electronic die and a first dielectric layer over the interconnect structure, where the electronic die is connected to the interconnect structure; a first substrate bonded to the electronic die and the first dielectric layer; a socket attached to a top surface of the first substrate; and a fiber holder coupled to the first substrate through the socket, where the fiber holder includes a prism that re-orients an optical path of an optical signal.Type: GrantFiled: May 5, 2023Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ming Weng, Chen-Hua Yu, Chung-Shi Liu, Hao-Yi Tsai, Cheng-Chieh Hsieh, Hung-Yi Kuo, Tsung-Yuan Yu, Hua-Kuei Lin, Che-Hsiang Hsu
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Patent number: 11935878Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.Type: GrantFiled: September 10, 2021Date of Patent: March 19, 2024Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Hsiu-Mei Yu, Guang-Yuan Jiang, Cheng-Yi Hsieh, Wei-Chan Chang, Chang-Sheng Lin
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Patent number: 11935841Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a device package and a shielding layer. The device package includes an electronic device unit and has a first surface, a second surface opposite to the first surface, and a third surface connecting the first surface to the second surface. The shielding layer is disposed on the first surface and the second surface of the device package. A common edge of the second surface and the third surface includes a first portion exposed from the shielding layer by a first length, and a common edge of the first surface and the third surface includes a second portion exposed from the shielding layer by a second length that is different from the first length.Type: GrantFiled: November 18, 2022Date of Patent: March 19, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Hung-Yi Lin, Meng-Wei Hsieh, Yu-Pin Tsai
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Patent number: 11935871Abstract: A semiconductor package including a first semiconductor die, a second semiconductor die, a first insulating encapsulation, a dielectric layer structure, a conductor structure and a second insulating encapsulation is provided. The first semiconductor die includes a first semiconductor substrate and a through silicon via (TSV) extending from a first side to a second side of the semiconductor substrate. The second semiconductor die is disposed on the first side of the semiconductor substrate. The first insulating encapsulation on the second semiconductor die encapsulates the first semiconductor die. A terminal of the TSV is coplanar with a surface of the first insulating encapsulation. The dielectric layer structure covers the first semiconductor die and the first insulating encapsulation. The conductor structure extends through the dielectric layer structure and contacts with the through silicon via.Type: GrantFiled: August 30, 2021Date of Patent: March 19, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Yi Tsai, Cheng-Chieh Hsieh, Tsung-Hsien Chiang, Hui-Chun Chiang, Tzu-Sung Huang, Ming-Hung Tseng, Kris Lipu Chuang, Chung-Ming Weng, Tsung-Yuan Yu, Tzuan-Horng Liu
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Patent number: 11923825Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. The semiconductor device includes a carrier, an element, and a first electronic component. The element is disposed on the carrier. The first electronic component is disposed above the element. The element is configured to adjust a first bandwidth of a first signal transmitted from the first electronic component.Type: GrantFiled: July 22, 2021Date of Patent: March 5, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Yuan Kung, Meng-Wei Hsieh
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Publication number: 20240069277Abstract: A semiconductor package includes a first die stack structure and a second die stack structure, an insulating encapsulation, a redistribution structure, at least one prism structure and at least one reflector. The first die stack structure and the second die stack structure are laterally spaced apart from each other along a first direction, and each of the first die stack structure and the second die stack structure comprises an electronic die; and a photonic die electronically communicating with the electronic die. The insulating encapsulation laterally encapsulates the first die stack structure and the second die stack structure. The redistribution structure is disposed on the first die stack structure, the second die stack structure and the insulating encapsulation, and electrically connected to the first die stack structure and the second die stack structure. The at least one prism structure is disposed within the redistribution structure and optically coupled to the photonic die.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Cheng-Chieh Hsieh, Che-Hsiang Hsu, Chung-Ming Weng, Tsung-Yuan Yu
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Patent number: 11850094Abstract: This invention provides an ultrasonic transducer with a zipper array of transducing elements, which includes a tail and a head. A surface of the head is embedded with a plurality of left transducing elements and a plurality of right transducing elements, wherein each left transducing element at least partially overlaps each right transducing element in an elevation axis.Type: GrantFiled: February 8, 2022Date of Patent: December 26, 2023Inventor: Cheng-Yuan Hsieh
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Publication number: 20220249059Abstract: This invention provides an ultrasonic transducer with a zipper array of transducing elements, which includes a tail and a head. A surface of the head is embedded with a plurality of left transducing elements and a plurality of right transducing elements, wherein each left transducing element at least partially overlaps each right transducing element in an elevation axis.Type: ApplicationFiled: February 8, 2022Publication date: August 11, 2022Inventor: Cheng-Yuan HSIEH
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Patent number: 11359874Abstract: A three dimensional pulsating heat pipe includes a three dimensional pipe coil structure and a heat exchange chamber. The three dimensional pipe coil structure is formed by winding at least one metal pipe to surround repeatedly a central axis and stack by extending along the central axis. Two opposite sides of the three dimensional pipe coil structure are arranged as a heating section and a condensation section, respectively. The heat exchange chamber is disposed at the heating section. Two opposite ends of the at least one metal pipe are connected with an interior of the heat exchange chamber.Type: GrantFiled: January 7, 2021Date of Patent: June 14, 2022Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Cheng-Yuan Hsieh, Chih-Yung Tseng
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Publication number: 20220120520Abstract: A three dimensional pulsating heat pipe includes a three dimensional pipe coil structure and a heat exchange chamber. The three dimensional pipe coil structure is formed by winding at least one metal pipe to surround repeatedly a central axis and stack by extending along the central axis. Two opposite sides of the three dimensional pipe coil structure are arranged as a heating section and a condensation section, respectively. The heat exchange chamber is disposed at the heating section. Two opposite ends of the at least one metal pipe are connected with an interior of the heat exchange chamber.Type: ApplicationFiled: January 7, 2021Publication date: April 21, 2022Inventors: CHENG-YUAN HSIEH, CHIH-YUNG TSENG
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Publication number: 20210093289Abstract: This invention provides an ultrasound system for improving needle visualization, including: an ultrasound transducer, which has a tail and a head. A plurality of transducing elements (or more specifically, piezoelectric elements) are embedded in a surface of the head. The transducing elements are arranged in an array of M multiplying N (M×N), wherein M is a positive even number, N is a positive integer, and N is greater than M.Type: ApplicationFiled: September 18, 2020Publication date: April 1, 2021Inventor: Cheng-Yuan HSIEH