Abstract: A display includes a display medium layer and a dielectric layer disposed at a side of the display medium layer. The composition of the dielectric layer includes at least a humectant for decreasing the electric resistivity of the dielectric layer and stabilizing the electric performance of the display.

Abstract: A display includes a display medium layer and a dielectric layer disposed at a side of the display medium layer. The composition of the dielectric layer includes at least a humectant for decreasing the electric resistivity of the dielectric layer and stabilizing the electric performance of the display.

Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on the substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced heat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.

Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on the substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced heat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.

Abstract: A new semiconductor packaging technology is proposed for the fabrication of a thermally-enhanced stacked-die BGA (Ball Grid Array) semiconductor package. By the proposed semiconductor packaging technology, a substrate is used as a chip carrier for the mounting of two semiconductor chips in conjunction with a heat spreader thereon, wherein the first semiconductor chip is mounted over the substrate through flip-chip (FC) technology; the heat spreader is mounted over the first semiconductor chip and supported on he substrate; and the second semiconductor chip is mounted on the heat spreader and electrically coupled to the substrate through wire-bonding (WB) technology. To facilitate the wire-bonding process, the heat spreader is formed with a plurality of wire-routing openings to allow the bonding wires to be routed therethrough. Since chip-produced beat during operation can be dissipated through the heat spreader, it allows an enhanced heat-dissipation efficiency.

Abstract: A semiconductor package is proposed, in which a lid is attached to a semiconductor chip and appropriately spaced apart from a heat sink having a top surface thereof exposed to the outside an encapsulant, so as to prevent external moisture from condensing on the semiconductor chip and reduce a thermal stress effect on the semiconductor chip. Moreover, a thermal conductive path is reduced in a portion passing through the encapsulant, allowing the heat-dissipating efficiency to be improved. In addition, with no contact between the heat sink and the semiconductor chip, quality of the semiconductor package is assured with no damage to the semiconductor chip.

Abstract: The present invention relates to a semiconductor package with a heat sink. There is at least one chip adhered to the substrate and the heat sink is constituted by a planar plate and a support for supporting the planar plate to a height for positioning the planar plate above the chip. The planar plate has a top surface exposed outside a resin body used for encapsulating the chip and the heat sink, and a bottom surface opposed to the top surface. The planar plate further has a thick portion formed on the bottom surface relative to the position of the chip, wherein there is a gap formed between the end surface of the thick portion and the chip to prevent the heat sink from directly contacting with the chip, and an end surface of the thick portion has a plurality of flow channels formed along the flowing direction of the molding gate to avoid the formation of void in the gap so as to increase the yield rate of products.

Abstract: A semiconductor package is proposed, in which a lid is attached to a semiconductor chip and appropriately spaced apart from a heat sink having a top surface thereof exposed to the outside an encapsulant, so as to prevent external moisture from condensing on the semiconductor chip and reduce a thermal stress effect on the semiconductor chip. Moreover, a thermal conductive path is reduced in a portion passing through the encapsulant, allowing the heat-dissipating efficiency to be improved. In addition, with no contact between the heat sink and the semiconductor chip, quality of the semiconductor package is assured with no damage to the semiconductor chip.

Abstract: A semiconductor package having a lead frame is provided in which the lead frame has a plurality of leads and a die pad for mounting a semiconductor die. The die pad is formed with at least one opening for exposing a portion of the surface of the semiconductor die. An encapsulant is formed to enclose the semiconductor die, portions of the leads and a portion of the die pad, while having a surface of the die pad to expose the form of the encapsulant. As a surface of the die pad is exposed to the exterior of the encapsulant, the opening formed on the die pad provides a thermal conduction path from the semiconductor die to the ambient, thereby enhancing the heat dissipation property of the semiconductor package.

Abstract: A semiconductor package includes a lead frame having a die pad for a semiconductor chip to be mounted thereon. The die pad is surrounded by a plurality of leads for electrically connecting the semiconductor chip and has one opening formed to decrease the attaching area between the semiconductor chip and the die pad so as to prevent the occurrence of declamination. A base pad is provided to be coupled to the die pad in such a manner that the base pad is positioned underneath or above the die pad and has a bottom surface or a top surface to be exposed to the extension of a resin encapsulant for enclosing the semiconductor chip and a portion of the lead frame, allowing the base pad to serve as a heat dissipater for transferring heat of the semiconductor package to the ambient.