Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a memory cell over a substrate, where the memory cell comprises a data storage structure. A conductive interconnect is over the data storage structure and comprises a first protrusion adjacent to a first side of the data storage structure, where the first protrusion comprises a flat bottom surface. A spacer structure is disposed on the first side of the data storage structure. The spacer structure directly contacts the flat bottom surface of the first protrusion.

Abstract: A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first substrate having an upper surface and a recessed surface extending in a closed loop around the upper surface. The recessed surface is vertically between the upper surface and a lower surface of the first substrate opposing the upper surface. A first plurality of interconnects are disposed within a first dielectric structure on the upper surface. A dielectric protection layer is over the recessed surface, along a sidewall of the first dielectric structure, and along a sidewall of the first substrate. The first substrate extends from directly below the dielectric protection layer to laterally outside of the dielectric protection layer.

Abstract: This disclosure describes systems, methods, and devices related to a distributed relay. The distributed relay may utilize beamforming and/or a specific physical arrangement of transmit and receive antennas to ensure a high isolation between antennas. The distributed relay may further facilitate the concurrent operation of two different intermediate frequency (IF) chains to support communications between a network entity and user device, receiving and transmitting data on each of the two IF chains independently of one another.

Abstract: A photographing optical lens system includes six lens elements. The six lens elements are, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element. The second lens element has negative refractive power. The third lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The fifth lens element has an image-side surface being concave in a paraxial region thereof. The sixth lens element has positive refractive power.

Abstract: A semiconductor structure is provided. The semiconductor structure includes metallization structure, a plurality of conductive pads, and a dielectric layer. The plurality of conductive pads is over the metallization structure. The dielectric layer is on the metallization structure and covers the conductive pad. The dielectric layer includes a first dielectric film, a second dielectric film, and a third dielectric film. The first dielectric film is on the conductive pad. The second dielectric film is on the first dielectric film. The third dielectric film is on the second dielectric film. The a refractive index of the first dielectric film is smaller than a refractive index of the second dielectric film, and the refractive index of the second dielectric film is smaller than a refractive index of the third dielectric film.

Abstract: A method includes forming image sensors in a semiconductor substrate, thinning the semiconductor substrate from a backside of the semiconductor substrate, forming a dielectric layer on the backside of the semiconductor substrate, and forming a polymer grid on the backside of the semiconductor substrate. The polymer grid has a first refractivity value. The method further includes forming color filters in the polymer grid, wherein the color filters has a second refractivity value higher than the first refractivity value, and forming micro-lenses on the color filters.

Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.

Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. In some embodiments, the RRAM device includes a first electrode disposed over a substrate and a second electrode over the first electrode. A doped data storage structure is disposed between the first electrode and the second electrode. The doped data storage structure has a dopant with a doping concentration profile that is asymmetric over a height of the doped data storage structure and that has a maximum dopant concentration at non-zero distances from a top surface and a bottom surface of the doped data storage structure.

Abstract: A chemical mechanical polishing composition for polishing a ruthenium containing substrate comprises, consists of, or consists essentially of a water based liquid carrier; titanium oxide particles dispersed in the liquid carrier, the titanium oxide particles including rutile and anatase such that an x-ray diffraction pattern of the titanium oxide particles has a ratio X:Y greater than about 0.05, wherein X represents an intensity of a peak in the x-ray diffraction pattern having a d-spacing of about 3.24 ? and Y represents an intensity of a peak in the x-ray diffraction pattern having a d-spacing of about 3.51 ?; and a pH in a range from about 7 to about 10. Optional embodiments further include a pH buffer having a pKa in a range from about 6 to about 9.

Abstract: A chemical mechanical polishing composition for polishing tungsten or molybdenum comprises, consists essentially of, or consists of a water based liquid carrier, abrasive particles dispersed in the liquid carrier, an amino acid selected from the group consisting of arginine, histidine, cysteine, lysine, and mixtures thereof, an anionic polymer or an anionic surfactant, and an optional amino acid surfactant. A method for chemical mechanical polishing a substrate including a tungsten layer or a molybdenum layer includes contacting the substrate with the above described polishing composition, moving the polishing composition relative to the substrate, and abrading the substrate to remove a portion of the tungsten layer or the molybdenum layer from the substrate and thereby polish the substrate.

Abstract: A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

Abstract: An assembly structure includes a core-computing section and a sub-computing section. The core-computing section has a first surface and a second surface opposite to the first surface. The core-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The sub-computing section has a first surface stacked on the first surface of the core-computing section and a second surface opposite to the first surface. The sub-computing section includes at least one conductive via electrically connecting the first surface and the second surface. The assembly structure includes a first signal transmission path and a second signal transmission path. The first signal transmission path is between the at least one conductive via of the sub-computing section and the at least one conductive via of the core-computing section.

Abstract: A lens antenna system is disclosed. The lens antenna system comprises a hybrid focal source antenna circuit configured to generate a source antenna beam for integration with different lens structures. In some embodiments, the hybrid focal source antenna circuit comprises a set of antenna elements coupled to one another. In some embodiments, the set of antenna elements comprises a first antenna element configured to be excited in a first spherical mode; and a second antenna element configured to be excited in a second, different, spherical mode. In some embodiments, the first spherical mode and the second spherical mode are co-polarized. In some embodiments, the lens antenna system further comprises a lens configured to shape the source antenna beam associated with the hybrid focal source antenna circuit, in order to provide an output antenna beam.

Abstract: The present disclosure relates to a semiconductor package and a method of manufacturing the same. In some embodiments, a semiconductor package includes a substrate, at least one die, a sealing ring and an inductor. The at least one die is mounted on the substrate and includes a plurality of component structures operating with acoustic waves. The component structures are arranged on a side of the at least one die that faces the substrate. The sealing ring is disposed between the at least one die and the substrate and surrounds the component structures. The inductor is disposed in the substrate.

Abstract: A system and method for forming pixels in an image sensor is provided. In an embodiment, a semiconductor device includes an image sensor including a first pixel region and a second pixel region in a substrate, the first pixel region being adjacent to the second pixel region. A first anti-reflection coating is over the first pixel region, the first anti-reflection coating reducing reflection for a first wavelength range of incident light. A second anti-reflection coating is over the second pixel region, the second anti-reflection coating reducing reflection for a second wavelength range of incident light that is different from the first wavelength range.

Abstract: The present disclosure, in some embodiments, relates to a multi-dimensional integrated chip structure. The multi-dimensional integrated chip structure includes a first substrate having a first upper surface and a second upper surface above the first upper surface. A first outermost perimeter of the first upper surface is larger than a second outermost perimeter of the second upper surface. A second substrate is over the first substrate. The second substrate has a third upper surface above the second upper surface. A third outermost perimeter of the third upper surface is smaller than the second outermost perimeter of the second upper surface.

Abstract: An interface connection method applied to a connection device. The connection device is configured to connect a host end having a first connection interface and a device end having a second connection interface. The interface connection method includes determining a voltage level of a detection pin; performing a first initialization when the detection pin is at a low level; providing an electrical power for detecting whether the electrical power is consumed or not when the detection pin is at a high level; sending a link signal when the electrical power is consumed; and performing a second initialization when the device end is detected to be in a ready state.

Abstract: An image sensor device is disclosed. The image sensor device includes: a substrate having a front surface and a back surface; a radiation-sensing region formed in the substrate; an opening extending from the back surface of the substrate into the substrate; a first metal oxide film including a first metal, the first metal oxide film being formed on an interior surface of the opening; and a second metal oxide film including a second metal, the second metal oxide film being formed over the first metal oxide film; wherein the electronegativity of the first metal is greater than the electronegativity of the second metal. An associated fabricating method is also disclosed.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.