Patents by Inventor Cheng Zheng

Cheng Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110162051
    Abstract: A computer readable storage medium has computer-executable instructions for causing a computer system to perform a method. The method includes receiving authentication information from an electronic device; identifying the electronic device based on device information for the electronic device; locating an entry associated with a combination of the authentication information and the electronic device, the entry including a count of the number of times the authentication information failed authentication during a specified time interval; and locking out the combination if the count reaches a threshold value, thus blocking the authentication information from accessing a target.
    Type: Application
    Filed: January 20, 2010
    Publication date: June 30, 2011
    Inventors: Yunfeng LI, Ke CHEN, Cheng ZHENG
  • Patent number: 7831762
    Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: November 9, 2010
    Assignee: Intel Corporation
    Inventor: Cheng Zheng
  • Publication number: 20080285332
    Abstract: Methods and apparatuses for storage of data in bit-alterable, non-volatile memories. In some embodiments, an array of memory locations implemented as bit-alterable, non-volatile memory configured as a plurality of blocks of memory locations; and control circuitry coupled with the array of memory locations to cause a block of data to be stored in the array of memory spanning a boundary between a first block of memory locations and a second block of memory locations. One or more processors access system data during initialization of an electronic system by retrieving data from a pre-selected location in a bit-alterable, non-volatile memory without scanning multiple memory locations to locate the system data.
    Type: Application
    Filed: December 30, 2005
    Publication date: November 20, 2008
    Inventors: Cheng Zheng, Hongyu Wang
  • Publication number: 20080123441
    Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 29, 2008
    Inventor: Cheng Zheng
  • Publication number: 20070233174
    Abstract: The present invention provides the filter from the wire elements only, which certainly traps the thrombus and others, and easily visualizes from extra-corporeal and trapping system. The solution set forth in the present invention involves an expandable trapping filter, which is consist of plural knitted metallic wires with elastic or shape memory nature. The filter has two bundled parts in the distal and proximal ends of plural wires. When this filter expands at the intended tubular cavity of body part, each wire flips over to form parasol shape moving proximal bundled to distal bundled to catch a thrombus and others. Trapping system is deliverable from the distal edge of sheath which is interiorly loaded and is able to move in and out by the shaft movement along the penetrating shaft with the of proximal bundle immobilization.
    Type: Application
    Filed: October 30, 2006
    Publication date: October 4, 2007
    Inventors: Gordon Hocking, Cheng Zheng Hui
  • Patent number: 6535208
    Abstract: A method and apparatus locks a plurality of display synchronization signals, such as horizontal synchronization signals and a vertical synchronization signals, from a plurality of display output devices, such as a plurality of graphics processors. The method and apparatus digitally adjusts a vertical synchronization signal associated with a first display output device, with respect to a vertical synchronization signal associated with a second graphic output device until a crossover is detected between the first and second vertical synchronization signals. This provides a type of coarse synchronization. In response to detection of the first crossover, the method and apparatus digitally adjusts a horizontal synchronization signal associated with the first display output device with respect to a horizontal synchronization signal associated with the second display device to align the synchronization signals. The adjustment of the horizontal synchronization signals provides a fine synchronization adjustment.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: March 18, 2003
    Assignee: Ati International Srl
    Inventors: Roumen Saltchev, Edward G. Callway, Zemin Liu, Jian-Cheng Zheng