Patents by Inventor Cheng Zheng

Cheng Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11610114
    Abstract: A method for employing a supervised graph sparsification (SGS) network to use feedback from subsequent graph learning tasks to guide graph sparsification is presented. The method includes, in a training phase, generating sparsified subgraphs by edge sampling from input training graphs following a learned distribution, feeding the sparsified subgraphs to a prediction/classification component, collecting a predication/classification error, and updating parameters of the learned distribution based on a gradient derived from the predication/classification error. The method further includes, in a testing phase, generating sparsified subgraphs by edge sampling from input testing graphs following the learned distribution, feeding the sparsified subgraphs to the prediction/classification component, and outputting prediction/classification results to a visualization device.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: March 21, 2023
    Inventors: Bo Zong, Jingchao Ni, Haifeng Chen, Cheng Zheng
  • Patent number: 11561389
    Abstract: A high spatial and temporal resolution synthetic aperture phase microscopy (HISTR-SAPM) system and methods are provided for sample imaging and metrology. The HISTR-SAPM system includes a sample-illumination path along which a first illumination beam propagates and a reference-beam path along which a second illumination beam propagates. A first digital micromirror device (DMD), a second DMD, and a first scanning objective lens are disposed in the sample-illumination path and at a first side adjacent to the sample. A second scanning objective lens passes the sample information to a beam splitter (BS), where the sample illumination beam and the reference-beam are combined to form an interferogram at a final image plane for imaging the sample. A Fourier spatial spectrum analysis and a synthetic aperture are then used to reconstruct a quantitative phase map of the sample with a high resolution and at a high-speed.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: January 24, 2023
    Assignee: The Chinese University of Hong Kong
    Inventors: Renjie Zhou, Cheng Zheng
  • Publication number: 20220326318
    Abstract: A current sensor includes: plate-shaped bus bars; a magnetic detection portion; and a shell holding the bus bars. The bus bars are arranged in a first direction. At least some of the bus bars have: a first conductor portion extending in the first direction; a second conductor portion connected to one end of the first conductor portion and extending in a second direction crossing the first direction; and a third conductor portion connected to the other end of the first conductor portion and extending in a third direction. The bus bars at least include first and second bus bars adjacent in the first direction, where the width of the first conductor portion is greater than the thickness thereof, and when viewed from the third direction, the first conductor portions of the first and second bus bars are spaced apart from each other by a certain distance in the second direction.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 13, 2022
    Inventors: Cheng Zheng, Xunyu Zhang
  • Patent number: 11385256
    Abstract: The present disclosure relates to an in-situ testing device including a measuring head, a drive mechanism, and a testing chamber. The testing chamber is provided with a first optical observation hole. The measuring head is provided with a second optical observation hole. The testing chamber is provided with an opening allowing the measuring head to pass. The testing chamber is further provided with a shielding door, and the drive mechanism is connected to the shielding door to drive the shielding door to move relative to the testing chamber, to open or cover the opening, thereby opening or closing the testing chamber.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: July 12, 2022
    Assignee: TSINGHUA UNIVERSITY
    Inventors: Qi-Kun Xue, Xiao-Peng Hu, Cheng Zheng, Xi Chen
  • Publication number: 20210299677
    Abstract: The present invention provides a magnetic bead purification system, including: a housing; a liquid path treatment system provided inside the housing, the liquid path treatment system being connectable to a reagent barrel and a waste liquid barrel; a sample addition needle group connected to the liquid path treatment system, the sample addition needle group being movable within the housing and connected to the liquid path treatment system, so as to receive a reagent from the liquid path treatment system or to discharge a waste liquid to the liquid path treatment system; a purification magnetic separation system, including a magnetic element, the purification magnetic separation system being controllable to apply a lateral magnetic force to a purification treatment position inside the housing or stop the application of the magnetic force by the magnetic element; and a purification station system movable between a purification treatment position inside the housing and a loading position outside the housing, the
    Type: Application
    Filed: April 26, 2019
    Publication date: September 30, 2021
    Applicant: Nanjing GenScript Biotech Co., Ltd.
    Inventors: Jinxin Zhu, Ruina He, Hong Qian, Tao Bai, Deming Li, Cheng Zheng, Guodong Chen
  • Publication number: 20210296453
    Abstract: A split gate structure is disclosed. The split gate structure includes a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 ? between a higher center portion and a lower periphery portion. The split gate structure effectively improves the breakdown performance and the IGSS performance. A power MOS device having the split gate structure and a manufacturing method of the split gate structure are also provided.
    Type: Application
    Filed: May 14, 2020
    Publication date: September 23, 2021
    Inventors: Yuan Cheng ZHENG, Xin Huan SHI
  • Patent number: 11127823
    Abstract: A split gate structure is disclosed. The split gate structure includes a first polysilicon, a characteristic oxide, and a second polysilicon sequentially disposed in a trench in a vertical direction upward from a bottom of the trench. An upper surface of the characteristic oxide has a height difference less than 1500 ? between a higher center portion and a lower periphery portion. The split gate structure effectively improves the breakdown performance and the IGSS performance. A power MOS device having the split gate structure and a manufacturing method of the split gate structure are also provided.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: September 21, 2021
    Assignee: HeJian Technology (Suzhou) Co., Ltd.
    Inventors: Yuan Cheng Zheng, Xin Huan Shi
  • Patent number: 11061567
    Abstract: A method for adaptively identifying flash memory type includes driving a flash memory interface according to a predetermined configuration and a predetermined protocol of the flash memory interface to send a reading command to a flash memory module to obtain a flash memory identity by successfully reading the flash memory module; changing at least one of the configuration and the interface protocol of the flash memory interface then performing the obtaining the flash memory identity again until all preset adjustments have been tried; and storing the obtained flash memory identity and a firmware corresponding to the obtained flash memory identity to a designated address of a non-volatile memory when the flash memory module is successful read. The above automated method can solve the disadvantages of high cost and low manufacturing flexibility caused by conventional manual identification and re-burning of eFuses.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: July 13, 2021
    Assignee: RAYMX MICROELECTRONICS, CORP.
    Inventors: Shuangxi Chen, Cheng Zheng
  • Publication number: 20210199586
    Abstract: A high spatial and temporal resolution synthetic aperture phase microscopy (HISTR-SAPM) system and methods are provided for sample imaging and metrology. The HISTR-SAPM system includes a sample-illumination path along which a first illumination beam propagates and a reference-beam path along which a second illumination beam propagates. A first digital micromirror device (DMD), a second DMD, and a first scanning objective lens are disposed in the sample-illumination path and at a first side adjacent to the sample. A second scanning objective lens passes the sample information to a beam splitter (BS), where the sample illumination beam and the reference-beam are combined to form an interferogram at a final image plane for imaging the sample. A Fourier spatial spectrum analysis and a synthetic aperture are then used to reconstruct a quantitative phase map of the sample with a high resolution and at a high-speed.
    Type: Application
    Filed: December 23, 2020
    Publication date: July 1, 2021
    Inventors: Renjie Zhou, Cheng Zheng
  • Publication number: 20210124489
    Abstract: The present disclosure provides a method for adaptively identifying flash memory type, comprising: driving a flash memory interface according to a predetermined configuration and a predetermined protocol of the flash memory interface to send a reading command to a flash memory module to obtain a flash memory identity by successfully reading the flash memory module; changing at least one of the configuration and the interface protocol of the flash memory interface then performing the obtaining the flash memory identity again until all preset adjustments have been tried; and storing the obtained flash memory identity and a firmware corresponding to the obtained flash memory identity to a designated address of a non-volatile memory when the flash memory module is successful read. The above automated method can solve the disadvantages of high cost and low manufacturing flexibility caused by conventional manual identification and re-burning of eFuses.
    Type: Application
    Filed: February 5, 2020
    Publication date: April 29, 2021
    Inventors: SHUANGXI CHEN, CHENG ZHENG
  • Publication number: 20210096155
    Abstract: The present disclosure relates to an in-situ testing device including a measuring head, a drive mechanism, and a testing chamber. The testing chamber is provided with a first optical observation hole. The measuring head is provided with a second optical observation hole. The testing chamber is provided with an opening allowing the measuring head to pass. The testing chamber is further provided with a shielding door, and the drive mechanism is connected to the shielding door to drive the shielding door to move relative to the testing chamber, to open or cover the opening, thereby opening or closing the testing chamber.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: QI-KUN XUE, XIAO-PENG HU, CHENG ZHENG, XI CHEN
  • Publication number: 20210049414
    Abstract: A method for employing a differentiable ranking based graph sparsification (DRGS) network to use supervision signals from downstream tasks to guide graph sparsification is presented. The method includes, in a training phase, generating node representations by neighborhood aggregation operators, generating sparsified subgraphs by top-k neighbor sampling from a learned neighborhood ranking distribution, feeding the sparsified subgraphs to a task, generating a prediction, and collecting a prediction error to update parameters in the generating and feeding steps to minimize an error, and, in a testing phase, generating node representations by neighborhood aggregation operators related to testing data, generating sparsified subgraphs by top-k neighbor sampling from a learned neighborhood ranking distribution related to the testing data, feeding the sparsified subgraphs related to the testing data to a task, and outputting prediction results to a visualization device.
    Type: Application
    Filed: July 23, 2020
    Publication date: February 18, 2021
    Inventors: Bo Zong, Cheng Zheng, Haifeng Chen
  • Publication number: 20200151563
    Abstract: A method for employing a supervised graph sparsification (SGS) network to use feedback from subsequent graph learning tasks to guide graph sparsification is presented. The method includes, in a training phase, generating sparsified subgraphs by edge sampling from input training graphs following a learned distribution, feeding the sparsified subgraphs to a prediction/classification component, collecting a predication/classification error, and updating parameters of the learned distribution based on a gradient derived from the predication/classification error. The method further includes, in a testing phase, generating sparsified subgraphs by edge sampling from input testing graphs following the learned distribution, feeding the sparsified subgraphs to the prediction/classification component, and outputting prediction/classification results to a visualization device.
    Type: Application
    Filed: November 6, 2019
    Publication date: May 14, 2020
    Inventors: Bo Zong, Jingchao Ni, Haifeng Chen, Cheng Zheng
  • Publication number: 20110162051
    Abstract: A computer readable storage medium has computer-executable instructions for causing a computer system to perform a method. The method includes receiving authentication information from an electronic device; identifying the electronic device based on device information for the electronic device; locating an entry associated with a combination of the authentication information and the electronic device, the entry including a count of the number of times the authentication information failed authentication during a specified time interval; and locking out the combination if the count reaches a threshold value, thus blocking the authentication information from accessing a target.
    Type: Application
    Filed: January 20, 2010
    Publication date: June 30, 2011
    Inventors: Yunfeng LI, Ke CHEN, Cheng ZHENG
  • Patent number: 7831762
    Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: November 9, 2010
    Assignee: Intel Corporation
    Inventor: Cheng Zheng
  • Publication number: 20080285332
    Abstract: Methods and apparatuses for storage of data in bit-alterable, non-volatile memories. In some embodiments, an array of memory locations implemented as bit-alterable, non-volatile memory configured as a plurality of blocks of memory locations; and control circuitry coupled with the array of memory locations to cause a block of data to be stored in the array of memory spanning a boundary between a first block of memory locations and a second block of memory locations. One or more processors access system data during initialization of an electronic system by retrieving data from a pre-selected location in a bit-alterable, non-volatile memory without scanning multiple memory locations to locate the system data.
    Type: Application
    Filed: December 30, 2005
    Publication date: November 20, 2008
    Inventors: Cheng Zheng, Hongyu Wang
  • Publication number: 20080123441
    Abstract: In bit alterable memories, a particular header of a particular block may be programmed to a particular code to indicate that the block is to be considered empty. This saves the time of resetting all the bits in both the header and the data section of the block.
    Type: Application
    Filed: November 29, 2006
    Publication date: May 29, 2008
    Inventor: Cheng Zheng
  • Publication number: 20070233174
    Abstract: The present invention provides the filter from the wire elements only, which certainly traps the thrombus and others, and easily visualizes from extra-corporeal and trapping system. The solution set forth in the present invention involves an expandable trapping filter, which is consist of plural knitted metallic wires with elastic or shape memory nature. The filter has two bundled parts in the distal and proximal ends of plural wires. When this filter expands at the intended tubular cavity of body part, each wire flips over to form parasol shape moving proximal bundled to distal bundled to catch a thrombus and others. Trapping system is deliverable from the distal edge of sheath which is interiorly loaded and is able to move in and out by the shaft movement along the penetrating shaft with the of proximal bundle immobilization.
    Type: Application
    Filed: October 30, 2006
    Publication date: October 4, 2007
    Inventors: Gordon Hocking, Cheng Zheng Hui
  • Patent number: 6535208
    Abstract: A method and apparatus locks a plurality of display synchronization signals, such as horizontal synchronization signals and a vertical synchronization signals, from a plurality of display output devices, such as a plurality of graphics processors. The method and apparatus digitally adjusts a vertical synchronization signal associated with a first display output device, with respect to a vertical synchronization signal associated with a second graphic output device until a crossover is detected between the first and second vertical synchronization signals. This provides a type of coarse synchronization. In response to detection of the first crossover, the method and apparatus digitally adjusts a horizontal synchronization signal associated with the first display output device with respect to a horizontal synchronization signal associated with the second display device to align the synchronization signals. The adjustment of the horizontal synchronization signals provides a fine synchronization adjustment.
    Type: Grant
    Filed: September 5, 2000
    Date of Patent: March 18, 2003
    Assignee: Ati International Srl
    Inventors: Roumen Saltchev, Edward G. Callway, Zemin Liu, Jian-Cheng Zheng