Abstract: A receptacle connector mounted to the printed circuit board, includes an insulative housing defining a mating tongue and a metallic shell enclosing the housing to form a mating cavity in which said mating tongue forwardly extends. A complementary plug connector includes a shell with a bull-nose tip. A metallic piece is mounted around a root of the mating tongue and equipped with a plurality of spring tangs to contact the relatively rigid bull-nose tip of the shell of the complementary connector for EMI/RFI protection.

Abstract: A receptacle connector mounted to a PCB, includes an insulative housing defining a mating tongue and a metallic shell enclosing the housing to form a mating cavity in which said mating tongue forwardly extends. A metallic shielding plate is embedded within a mid-level of the mating tongue wherein a leg of the shielding plate and a tail of an outermost grounding contact share the same conductive grounding region on the PCB. A plug connector mateable with the receptacle connector, includes an insulative housing defining a mating cavity to receive the mating tongue and equipped with a plurality of contacts and a metallic latch beside the mating cavity, wherein a tail of one grounding contact and a leg of the latch share the same conductive grounding region on a paddle card, which is behind the mating cavity and on which tails of the contacts are electrically and mechanically mounted.

Abstract: A receptacle connector mounted to the printed circuit board, includes an insulative housing defining a mating tongue and a metallic shell enclosing the housing to form a mating cavity in which said mating tongue forwardly extends. A complementary plug connector includes a shell with a bull-nose tip. A metallic piece is mounted around a root of the mating tongue and equipped with a plurality of spring tangs to contact the relatively rigid bull-nose tip of the shell of the complementary connector for EMI/RFI protection.

Abstract: An electrical connector assembly includes plural wafers and the corresponding shielding plates are alternately stacked with one another. Each wafer includes a conductive housing defining plural slots therein, and plural terminal modules received in the corresponding slots, respectively. Each of the terminal modules includes a pair of differential contacts and an insulative holder retaining the pair of differential contacts. A plurality of cable assemblies correspond to the corresponding wafers. Each cable assemblies includes a plurality of cables each including a pair of differential wires respectively connected to the pair of differential contacts, respectively.

Abstract: A receptacle connector mounted to the printed circuit board, includes an insulative housing defining a mating tongue and a metallic shell enclosing the housing to form a mating cavity in which said mating tongue forwardly extends. A complementary plug connector includes a shell with a bull-nose tip. A metallic piece is mounted around a root of the mating tongue and equipped with a plurality of spring tangs to contact the relatively rigid bull-nose tip of the shell of the complementary connector for EMI/RFI protection.

Abstract: A primary connector (10, 20) includes a primary housing (11, 31) and a number of terminal groups. The primary housing includes a periphery wall (111, 311) and a side wall (112, 312) disposed at opposite sides of the primary housing and extending along a longitudinal direction, a slot (113, 313) defined between the periphery wall and the side wall, and a number of passageways (114, 314) extending along a transverse direction for receiving the number of terminal groups. Each terminal group includes a predetermined terminal (22, 42) having a contact section (221, 421) exposed to the slot and a pair of soldering portions (222, 422) respectively extending from opposite sides of the contact section and inserted outwardly from the periphery wall and the side wall.

Abstract: A primary connector (10, 20) includes a primary housing (11, 31) and a number of terminal groups. The primary housing includes a periphery wall (111, 311) and a side wall (112, 312) disposed at opposite sides of the primary housing and extending along a longitudinal direction, a slot (113, 313) defined between the periphery wall and the side wall, and a number of passageways (114, 314) extending along a transverse direction for receiving the number of terminal groups. Each terminal group includes a predetermined terminal (22, 42) having a contact section (221, 421) exposed to the slot and a pair of soldering portions (222, 422) respectively extending from opposite sides of the contact section and inserted outwardly from the periphery wall and the side wall.

Abstract: A receptacle connector mounted to a PCB, includes an insulative housing defining a mating tongue and a metallic shell enclosing the housing to form a mating cavity in which said mating tongue forwardly extends. A metallic shielding plate is embedded within a mid-level of the mating tongue wherein a leg of the shielding plate and a tail of an outermost grounding contact share the same conductive grounding region on the PCB. A plug connector mateable with the receptacle connector, includes an insulative housing defining a mating cavity to receive the mating tongue and equipped with a plurality of contacts and a metallic latch beside the mating cavity, wherein a tail of one grounding contact and a leg of the latch share the same conductive grounding region on a paddle card, which is behind the mating cavity and on which tails of the contacts are electrically and mechanically mounted.

Abstract: Embodiments provide for monitoring of an online user experience and/or remediating performance issues, but are not so limited. A computer-implemented method of an embodiment operates to receive, pre-aggregate, and aggregate client performance data as part of providing an end-to-end diagnostics monitoring and resolution service. A system of an embodiment is configured to aggregate performance data of a plurality of client devices or systems as part of identifying latency issues at one or more of a tenant level, geographic location level, and/or service provider level. Other embodiments are included.

Abstract: A receptacle connector mounted to the printed circuit board, includes an insulative housing defining a mating tongue and a metallic shell enclosing the housing to form a mating cavity in which said mating tongue forwardly extends. A complementary plug connector includes a shell with a bull-nose tip. A metallic piece is mounted around a root of the mating tongue and equipped with a plurality of spring tangs to contact the relatively rigid bull-nose tip of the shell of the complementary connector for EMI/RFI protection.

Abstract: A vehicle seat has a seat back and a seat cushion and a pair of recliners hingedly mounting the seat back to the seat cushion providing pivotal movement of a seat back relative to a seat cushion. Each of the recliners has a memory plate that holds the recliners in an unlocked condition during a predetermined amount of travel enabling return movement of the seat back from a forwardly folded position to a memory position. The memory position being within a range of recline seatback positions.

Abstract: A vehicle seat has a seat back and a seat cushion and a pair of recliners hingedly mounting the seat back to the seat cushion providing pivotal movement of a seat back relative to a seat cushion. Each of the recliners has a memory plate that holds the recliners in an unlocked condition during a predetermined amount of travel enabling return movement of the seat back from a forwardly folded position to a memory position. The memory position being within a range of recline seatback positions.

Abstract: Patterns with feature sizes of less than 50 microns are rapidly formed directly in semiconductors, particularly silicon, GaAs, indium phosphide, or single crystalline sapphire, using ultraviolet laser ablation. These patterns include very high aspect ratio cylindrical through-hole openings for integrated circuit connections; singulation of processed die contained on semiconductor wafers; and microtab cutting to separate microcircuit workpieces from a parent semiconductor wafer. Laser output pulses (32) from a diode-pumped, Q-switched frequency-tripled Nd:YAG, Nd:YVO4, or Nd:YLF is directed to the workpiece (12) with high speed precision using a compound beam positioner. The optical system produces a Gaussian spot size, or top hat beam profile, of about 10 microns. The pulse energy used for high-speed ablative processing of semiconductors using this focused spot size is greater than 200 ?J per pulse at pulse repetition frequencies greater than 5 kHz and preferably above 15 kHz.

Abstract: Patterns with feature sizes of less than 50 microns are rapidly formed directly in semiconductors, particularly silicon, GaAs, indium phosphide, or single crystalline sapphire, using ultraviolet laser ablation. These patterns include very high aspect ratio cylindrical through-hole openings for integrated circuit connections; singulation of processed die contained on semiconductor wafers; and microtab cutting to separate microcircuit workpieces from a parent semiconductor wafer. Laser output pulses (32) from a diode-pumped, Q-switched frequency-tripled Nd:YAG, Nd:YVO4, or Nd:YLF is directed to the workpiece (12) with high speed precision using a compound beam positioner. The optical system produces a Gaussian spot size, or top hat beam profile, of about 10 microns. The pulse energy used for high-speed ablative processing of semiconductors using this focused spot size is greater than 200 ?J per pulse at pulse repetition frequencies greater than 5 kHz and preferably above 15 kHz.

Abstract: UV laser cutting throughput through silicon and like materials is improved by dividing a long cut path (112) into short segments (122), from about 10 &mgr;m to 1 mm. The laser output (32) is scanned within a first short segment (122) for a predetermined number of passes before being moved to and scanned within a second short segment (122) for a predetermined number of passes. The bite size, segment size (126), and segment overlap (136) can be manipulated to minimize the amount and type of trench backfill. Real-time monitoring is employed to reduce rescanning portions of the cut path 112 where the cut is already completed. Polarization direction of the laser output (32) is also correlated with the cutting direction to further enhance throughput. This technique can be employed to cut a variety of materials with a variety of different lasers and wavelengths.

Abstract: UV laser cutting throughput through silicon and like materials is improved by dividing a long cut path (112) into short segments (122), from about 10 &mgr;m to 1 mm. The laser output (32) is scanned within a first short segment (122) for a predetermined number of passes before being moved to and scanned within a second short segment (122) for a predetermined number of passes. The bite size, segment size (126), and segment overlap (136) can be manipulated to minimize the amount and type of trench backfill. Real-time monitoring is employed to reduce rescanning portions of the cut path 112 where the cut is already completed. Polarization direction of the laser output (32) is also correlated with the cutting direction to further enhance throughput. This technique can be employed to cut a variety of materials with a variety of different lasers and wavelengths.

Abstract: Patterns with feature sizes of less than 50 microns are rapidly formed directly in semiconductors, particularly silicon, using ultraviolet laser ablation. These patterns include very high aspect ratio cylindrical through-hole openings for integrated circuit connections; singulation of processed die contained on semiconductor wafers; and microtab cutting to separate microcircuit workpieces from a parent semiconductor wafer. Laser output pulses (32) from a diode-pumped, Q-switched frequency-tripled Nd:YAG, Nd:YVO4, or Nd:YLF is directed to the workpiece (12) with high speed precision using a compound beam positioner. The optical system produces a Gaussian spot size, or top hat beam profile, of about 10 microns. The pulse energy used for high-speed ablative processing of silicon using this focused spot size is greater than 200 &mgr;J per pulse at pulse repetition frequencies greater than 5 kHz and preferably above 15 kHz.

Abstract: UV laser cutting throughput through silicon and like materials is improved by dividing a long cut path (112) into short segments (122), from about 10 ?m to 1 mm. The laser output (32) is scanned within a first short segment (122) for a predetermined number of passes before being moved to and scanned within a second short segment (122) for a predetermined number of passes. The bite size, segment size (126), and segment overlap (136) can be manipulated to minimize the amount and type of trench backfill. Real-time monitoring is employed to reduce rescanning portions of the cut path 112 (112) where the cut is already completed. Polarization direction of the laser output (32) is also correlated with the cutting direction to further enhance throughput. This technique can be employed to cut a variety of materials with a variety of different lasers and wavelengths. A multi-step process can optimize the laser processes for each individual layer.

Abstract: UV laser cutting throughput through silicon and like materials is improved by dividing a long cut path (112) into short segments (122), from about 10 ?m to 1 mm. The laser output (32) is scanned within a first short segment (122) for a predetermined number of passes before being moved to and scanned within a second short segment (122) for a predetermined number of passes. The bite size, segment size (126), and segment overlap (136) can be manipulated to minimize the amount and type of trench backfill. Real-time monitoring is employed to reduce rescanning portions of the cut path 112 (112) where the cut is already completed. Polarization direction of the laser output (32) is also correlated with the cutting direction to further enhance throughput. This technique can be employed to cut a variety of materials with a variety of different lasers and wavelengths. A multi-step process can optimize the laser processes for each individual layer.

Abstract: UV laser cutting throughput through silicon and like materials is improved by dividing a long cut path (112) into short segments (122), from about 10 ?m to 1 mm. The laser output (32) is scanned within a first short segment (122) for a predetermined number of passes before being moved to and scanned within a second short segment (122) for a predetermined number of passes. The bite size, segment size (126), and segment overlap (136) can be manipulated to minimize the amount and type of trench backfill. Real-time monitoring is employed to reduce rescanning portions of the cut path 112 (112) where the cut is already completed. Polarization direction of the laser output (32) is also correlated with the cutting direction to further enhance throughput. This technique can be employed to cut a variety of materials with a variety of different lasers and wavelengths. A multi-step process can optimize the laser processes for each individual layer.