Abstract: An array substrate includes a first electrode, scanning lines extending along a first direction, data lines, and common signal lines. The data lines and the common signal lines extend along a second direction. The first electrode includes a first and a second sub-electrode. Each data line is disposed between two common signal lines. Two scanning lines, two common signal lines, and a data line define a first and a second sub-pixel area. The first and the second sub-electrode are disposed within the first and the second sub-pixel area respectively. The first sub-electrode includes a first main portion disposed close to a common signal line and first branch portions spaced along the second direction. A first space is defined between two adjacent first branch portions. Ends of the first branch portions are connected to the first main portion. Another ends of the first branch portions are spaced with a first space.

Abstract: An embodiment of the present application discloses a pixel unit of a display panel and a display panel, wherein data lines are covered with a light shielding matrix element, two light shielding strips of the light shielding matrix element shield the two data lines respectively. Each light shielding strip comprises a first light shielding section and a second light shielding section in different widths overlap side edges of the main pixel electrode portion and side edges of the sub-pixel electrode portion respectively to effectively shield light leakage regions between the data lines and the pixel electrode, which solves the technical issue of the conventional pixel unit of a display panel forming light leakage regions between data lines and the pixel electrode, causing light leakage in a dark state, and resulting lowered display quality of the display panel and improves display quality.

Abstract: Embodiments of this application disclose a display panel. A primary pixel electrode is disposed inside a primary pixel region, and a sub-pixel electrode is disposed inside a sub-pixel region. First shading strips and second shading strips are intersected to form a plurality of primary frame bodies. One primary frame body correspondingly encloses a circumferential side of one pixel region. A third shading strip is disposed inside the primary frame body and correspondingly disposed between the primary pixel region and the sub-pixel region. The third shading strip and the primary frame body define two sub-frame bodies, and a channel for making the two sub-frame bodies communicate is disposed on the third shading strip.

Abstract: The present application discloses a pixel unit of a display panel, a lower substrate of a display panel, and a display panel. The present application by disposing a transparent shielding electrode element connected to a common signal line and extending into the aperture region and making an orthogonal projection of the transparent shielding electrode element on a plane where the common signal line is located at least partially overlap the common signal line, extends a shielding effect provided by the common signal line such that a parasitic capacitor between the pixel electrode and the data line is lowered.

Abstract: An embodiment of the present application discloses a pixel unit of a display panel and a display panel, wherein data lines are covered with a light shielding matrix element, two light shielding strips of the light shielding matrix element shield the two data lines respectively. Each light shielding strip comprises a first light shielding section and a second light shielding section in different widths overlap side edges of the main pixel electrode portion and side edges of the sub-pixel electrode portion respectively to effectively shield light leakage regions between the data lines and the pixel electrode, which solves the technical issue of the conventional pixel unit of a display panel forming light leakage regions between data lines and the pixel electrode, causing light leakage in a dark state, and resulting lowered display quality of the display panel and improves display quality.

Abstract: Embodiments of this application disclose a display panel. A primary pixel electrode is disposed inside a primary pixel region, and a sub-pixel electrode is disposed inside a sub-pixel region. First shading strips and second shading strips are intersected to form a plurality of primary frame bodies. One primary frame body correspondingly encloses a circumferential side of one pixel region. A third shading strip is disposed inside the primary frame body and correspondingly disposed between the primary pixel region and the sub-pixel region. The third shading strip and the primary frame body define two sub-frame bodies, and a channel for making the two sub-frame bodies communicate is disposed on the third shading strip.

Abstract: The present application provides an array substrate and a display device. The array substrate includes a first conductive layer, a second conductive layer, and an insulating layer. The first conductive layer includes at least two first conductive members disposed side by side in the bonding area. The second conductive layer includes at least two second conductive members; each of the second conductive members is provided corresponding to and electrically connected to each of the first conductive members, and at least two of the second conductive members and at least two of the first conductive members are electrically connected through a same via-hole on the insulating layer.

Abstract: The present invention provides a display panel and an electronic device. A gate driver on array (GOA) circuit in the display panel includes a plurality of cascaded GOA units. The GOA units include a plurality of effective GOA units and 2m redundant GOA units arranged in sequence. The plurality of effective GOA units forms a plurality of effective GOA modules that are arranged in sequence. In the effective GOA module, the 2m effective GOA units are sequentially connected to the 2m clock signal lines, and the 2m redundant GOA units are sequentially connected to the 2m clock signal lines. The display panel of the present invention has no periodic dark lines at low gray levels.

Abstract: The present invention provides a display panel and an electronic device. A gate driver on array (GOA) circuit in the display panel includes a plurality of cascaded GOA units. The GOA units include a plurality of effective GOA units and 2m redundant GOA units arranged in sequence. The plurality of effective GOA units forms a plurality of effective GOA modules that are arranged in sequence. In the effective GOA module, the 2m effective GOA units are sequentially connected to the 2m clock signal lines, and the 2m redundant GOA units are sequentially connected to the 2m clock signal lines. The display panel of the present invention has no periodic dark lines at low gray levels.

Abstract: The present application provides an array substrate and a display device. The array substrate includes a first conductive layer, a second conductive layer, and an insulating layer. The first conductive layer includes at least two first conductive members disposed side by side in the bonding area. The second conductive layer includes at least two second conductive members; each of the second conductive members is provided corresponding to and electrically connected to each of the first conductive members, and at least two of the second conductive members and at least two of the first conductive members are electrically connected through a same via-hole on the insulating layer.

Abstract: A color-filter on array (COA) display panel is provided. The COA display panel includes an array substrate, a color filter substrate disposed opposite to the array substrate, a component layer disposed on the array substrate, and a color resist layer covering the component layer; wherein the color resist layer is configured with at least one through hole, and an edge of an opening of the at least one through hole is arc-shaped.

Abstract: Provided are a COA array substrate and a display device. The array substrate is provided with a base layer, a metal layer, and a color resist layer from bottom to top. The array substrate is further provided with contact holes passing through the color resist layer and in contact with the metal layer, and the contact holes are arranged so that the alignment film droplets can be distributed when the alignment film droplets drop right onto the contact holes. Air bubbles as in the prior art are thus avoided, thereby preventing a cell gap due to accumulation of an alignment film from becoming larger. Thus, a luminance difference is avoided and the quality of the product is improved without upgrading the existing equipment. The brightness uniformity of the display device is improved by using the array substrate.

Abstract: A DLS array substrate and the display device thereof are disclosed. The DLS array substrate includes a substrate and at least one display pixel arranged on the substrate. The display pixel includes a plurality of first pixels and a plurality of second pixels arranged along a row direction and a column direction. The first pixel and the second pixel share the same data line but connect to different scanning lines. The first pixels and the second pixels are arranged periodically along the row direction and the column direction, and the period along the row direction or the column direction includes three or four display pixels. The period along at least the row direction or at least the column direction includes three display pixels. With such configuration, the signals delay effect regarding the DLS may be alleviated, and the bright and dark lines issue may be overcome.

Abstract: Provided are a COA array substrate and a display device. The array substrate is provided with a base layer, a metal layer, and a color resist layer from bottom to top. The array substrate is further provided with contact holes passing through the color resist layer and in contact with the metal layer, and the contact holes are arranged so that the alignment film droplets can be distributed when the alignment film droplets drop right onto the contact holes. Air bubbles as in the prior art are thus avoided, thereby preventing a cell gap due to accumulation of an alignment film from becoming larger. Thus, a luminance difference is avoided and the quality of the product is improved without upgrading the existing equipment. The brightness uniformity of the display device is improved by using the array substrate.

Abstract: A color-filter on array (COA) display panel is provided. The COA display panel includes an array substrate, a color filter substrate disposed opposite to the array substrate, a component layer disposed on the array substrate, and a color resist layer covering the component layer; wherein the color resist layer is configured with at least one through hole, and an edge of an opening of the at least one through hole is arc-shaped.

Abstract: A method for manufacturing a color-filter-on-array (COA) type liquid crystal panel, and a COA type liquid crystal panel are provided. By arranging the film formation and patterning of a color resist layer before a second metal layer, a hole is bored in a third insulative layer so as to form a via hole structure. Therefore, boring on the color resist layer is avoided, the manufacturing process thereof is simplified, and the pixel aperture ratio is improved.

Abstract: An array substrate including a plurality of pixel cells, at least one common electrode line, at least one data line, and at least one first scanning line and second scanning line parallel to the first scanning line is disclosed. The first scanning line and the second scanning line intersect with the data line. The pixel cell includes a first pixel electrode, a second pixel electrode, a first transistor, a second transistor, a third transistor, and a control circuit. In addition, a liquid crystal display is also disclosed. By adding one control circuit, the color shift effect in wide viewing angle is enhanced and the image sticking is eliminated.

Abstract: A DLS array substrate and the display device thereof are disclosed. The DLS array substrate includes a substrate and at least one display pixel arranged on the substrate. The display pixel includes a plurality of first pixels and a plurality of second pixels arranged along a row direction and a column direction. The first pixel and the second pixel share the same data line but connect to different scanning lines. The first pixels and the second pixels are arranged periodically along the row direction and the column direction, and the period along the row direction or the column direction includes three or four display pixels. The period along at least the row direction or at least the column direction includes three display pixels. With such configuration, the signals delay effect regarding the DLS may be alleviated, and the bright and dark lines issue may be overcome.

Abstract: The present invention provides a display panel and driving method thereof, and display device. The display panel includes an array substrate and a color filter substrate, disposed oppositely; the array substrate comprising a plurality of scan lines, disposed at intervals; a plurality of data line, disposed at intervals, and crossing over and isolated from the scan lines; and a plurality of pixel units, arranged in a matrix form, and driven by the scan lines and data lines; each of the pixel units further divided into at least two active areas; the color filter substrate includes at least two common electrodes, disposed correspondingly to the active areas, the at least two common electrodes applying common voltages independently. The present invention can eliminate the non-uniform luminance problem in display images and improve the display quality.

Abstract: Disclosed are a display device and the manufacturing method thereof. In the display device, the pixel unit of the display substrate comprises: a gate line material layer, a transparent electrode layer, a semiconductor layer, and a metal layer; the semiconductor layer and the metal layer are disposed between the gate line material layer and the transparent electrode layer; the metal layer is located above the semiconductor layer. The present invention could cause the storage capacitor of the display device to be smaller, thereby reducing the RC delay of the scanning signal of the gate line.