Abstract: The present disclosure provides a semiconductor sensing device. The semiconductor sensing device includes a substrate having a sensing region. The sensing region includes an active feature. The active feature includes an anchor portion, an elevated portion, and a nanowire portion. The anchor portion is on a top surface of the substrate. The elevated portion is spaced from the top surface of the substrate by a vertical distance and connected to the anchor portion. The nanowire portion is on the top surface of the substrate and connected to the anchor portion. The vertical distance is greater than or equal to a thickness of the nanowire portion.

Abstract: Features related to systems and methods for automated generation of a machine learning model based in part on a pretrained model are described. The pretrained model is used as a starting point to augment and retrain according to client specifications. The identification of an appropriate pretrained model is based on the client specifications such as model inputs, model outputs, and similarities between the data used to train the models.

Abstract: Techniques are described automatically determining runtime configurations used to execute recurrent neural networks (RNNs) for training or inference. One such configuration involves determining whether to execute an RNN in a looped, or “rolled,” execution pattern or in a non-looped, or “unrolled,” execution pattern. Execution of an RNN using a rolled execution pattern generally consumes less memory resources than execution using an unrolled execution pattern, whereas execution of an RNN using an unrolled execution pattern typically executes faster. The configuration choice thus involves a time-memory tradeoff that can significantly affect the performance of the RNN execution. This determination is made automatically by a machine learning (ML) runtime by analyzing various factors such as, for example, a type of RNN being executed, the network structure of the RNN, characteristics of the input data to the RNN, an amount of computing resources available, and so forth.

Abstract: Provided is a method for manufacturing a semiconductor device, including: forming a conductive layer on the first dielectric layer; forming a recess in the conductive layer; performing a first etching process to round a top corner of the recess; performing a second etching process to remove the conductive layer exposed from a bottom surface of the recess and thereby forming an opening having a rounding top corner in the conductive layer; and forming a second dielectric layer in the opening.

Abstract: The present disclosure provides a semiconductor sensing device. The semiconductor sensing device includes a substrate having a sensing region. The sensing region includes an active feature. The active feature includes an anchor portion, an elevated portion, and a nanowire portion. The anchor portion is on a top surface of the substrate. The elevated portion is spaced from the top surface of the substrate by a vertical distance and connected to the anchor portion. The nanowire portion is on the top surface of the substrate and connected to the anchor portion. The vertical distance is greater than or equal to a thickness of the nanowire portion.

Abstract: Present disclosure provides a method for multi-level etch. The method includes providing a substrate, forming a first reference feature over a control region of the substrate, forming an etchable layer over the first reference feature and a target region over the substrate, patterning a masking layer over the etchable layer, the masking layer having a first opening projecting over the control region and a second opening projecting over the target region, and removing a portion of the etchable layer through the first opening and the second opening until the first reference feature is reached. A semiconductor sensing device manufactured by the multi-level etch is also disclosed.

Abstract: Provided is a method for manufacturing a semiconductor device, including: forming a conductive layer on the first dielectric layer; forming a recess in the conductive layer; performing a first etching process to round a top corner of the recess; performing a second etching process to remove the conductive layer exposed from a bottom surface of the recess and thereby forming an opening having a rounding top corner in the conductive layer; and forming a second dielectric layer in the opening.

Abstract: Present disclosure provides a method for multi-level etch. The method includes providing a substrate, forming a first reference feature over a control region of the substrate, forming an etchable layer over the first reference feature and a target region over the substrate, patterning a masking layer over the etchable layer, the masking layer having a first opening projecting over the control region and a second opening projecting over the target region, and removing a portion of the etchable layer through the first opening and the second opening until the first reference feature is reached. A semiconductor sensing device manufactured by the multi-level etch is also disclosed.

Abstract: The method of operation of a meter includes placing a sample on a test strip, assigning a first electrode of the test strip to be a counter electrode, applying a first signal to the test strip during a first period of time, assigning a second electrode of the test strip to be the counter electrode, applying a second signal to the test strip to measure the concentration of an analyte in the sample.

Abstract: The method of operation of a meter includes placing a sample on a test strip, assigning a first electrode of the test strip to be a counter electrode, applying a first signal to the test strip during a first period of time, assigning a second electrode of the test strip to be the counter electrode, applying a second signal to the test strip to measure the concentration of an analyte in the sample.

Abstract: A test strip includes a substrate, a spacer layer having a notch, a reagent layer, a support layer, and a cover layer having a covering portion covering the notch and a channel portion extending rearward from the covering portion corresponding to a rear end of the notch. The substrate is attached under the spacer layer and has a reaction region exposed from the notch. The support layer is located at two sides of the notch and connected to the cover layer and the spacer layer to make the channel portion away from the spacer layer at a vertical distance. The support layer, the covering portion, the notch, and the substrate form a reaction chamber for allowing an analyte solution to react with the reagent layer coated on the reaction region, and the support layer, the channel portion, and the spacer layer forms a channel for exhausting air.

Abstract: A method of a test strip detecting concentration of an analyte of a sample includes placing the sample in a reaction region of the test strip, wherein the analyte reacts with an enzyme to generate a plurality of electrons, and the plurality of electrons are transferred to a working electrode of the reaction region through a mediator; applying an electrical signal to the working electrode; measuring a first current through the working electrode during a first period; the mediator generating an intermediate according to the electrical signal during a second period; measuring a second current through the working electrode during a third period; calculating initial concentration of the analyte according to the first current; calculating a diffusion factor of the intermediate in the sample according to the second current; and correcting the initial concentration to generate new concentration of the analyte according to the diffusion factor.

Abstract: The present invention discloses a biological measuring device with auto coding capabilities. In accordance with one embodiment of the present invention, the biological measuring device with auto coding capabilities includes a test strip having a substrate and at least a first contact pad and a second contact pad provided on the substrate; and a code reader having at least a first metal pin and a second metal pin to couple to the first contact pad and the second contact pad to obtain coding information associated with the test strip, wherein the code reader is capable of reading the coding information based on a movement of the test strip before the test strip is placed still in relation to the code reader for a proper reading of a sample.

Abstract: The present invention discloses a method for fabricating an optical filter based on polymer asymmetric bragg couplers using holographic interference techniques, soft lithography, and micro molding, which comprises following steps: prepare a UV polymer with gratings; coating photo-resister film on the UV polymer, and exposed by UV light to obtain a photo-resister mold with two grooves each having gratings; coating diluted PDMS film on the photo-resister mold, and baking the PDMS film to obtain a PDMS mold having two waveguides with gratings; placing glass substrate over the PDMS mold to form a first tunnel; injecting a precure UV polymer into the first tunnel to from a cladding layer with two grooves having gratings pattern at its bottom; placing glass slide over the cladding layer and injecting a mixed UV polymer into the grooves to form waveguide cores; placing a second glass substrate over the cladding layer, and injecting UV polymer to form an upper cladding layer laminated with the cladding layer to obtai

Abstract: The present invention discloses a biological measuring device with auto coding capabilities. In accordance with one embodiment of the present invention, the biological measuring device with auto coding capabilities includes a test strip having a substrate and at least a first contact pad and a second contact pad provided on the substrate; and a code reader having at least a first metal pin and a second metal pin to couple to the first contact pad and the second contact pad to obtain coding information associated with the test strip, wherein the code reader is capable of reading the coding information based on a movement of the test strip before the test strip is placed still in relation to the code reader for a proper reading of a sample.

Abstract: The present invention discloses a method for fabricating an optical filter based on polymer asymmetric bragg couplers using holographic interference techniques, soft lithography, and micro molding, which comprises following steps: prepare a UV polymer with gratings; coating photo-resister film on the UV polymer, and exposed by UV light to obtain a photo-resister mold with two grooves each having gratings; coating diluted PDMS film on the photo-resister mold, and baking the PDMS film to obtain a PDMS mold having two waveguides with gratings; placing glass substrate over the PDMS mold to form a first tunnel; injecting a precure UV polymer into the first tunnel to from a cladding layer with two grooves having gratings pattern at its bottom; placing glass slide over the cladding layer and injecting a mixed UV polymer into the grooves to form waveguide cores; placing a second glass substrate over the cladding layer, and injecting UV polymer to form an upper cladding layer laminated with the cladding layer to obtai

Abstract: The present invention discloses a method for fabricating polymer wavelength filter with high-resolution periodical structure, which comprises: a positive photo-resister film is coated or a substrate, holographically exposed with grating pattern, and coated with a negative photo-resister film, then exposed by UV light and developed to obtain a waveguide mold having negative waveguide; a PDMS film coated on the waveguide mold, baked and peeled off to obtain a PDMS mold; a first tunnel formed over the PDMS mold, injected with a first UV polymer, then cured and separated the first UV polymer having groove to be the cladding layer of the polymer wavelength filter; a second UV polymer injected into the groove of the cladding layer, and cured to form the core of the waveguide in the groove of the cladding layer to finally be the polymer wavelength filter.

Abstract: The present invention discloses a method for fabricating polymeric wavelength filter, which method for forming gratings patterns on the UV polymer involves three processing steps. First, a gratings pattern is holographically exposed using a two-beam interference pattern on a positive photo-resister film. A 20-nm-thick nickel thin film is then sputtered onto the positive photo-resister film to form a nickel mold. This nickel mold on the photo-resister film then can be subsequently used to transfer the final gratings pattern onto a UV cure epoxy polymer. Whereby, a polymer film can be spun coated on the cure epoxy substrate so as to simplify the fabrication process for obtaining a polymer wavelength filter with good aspect ratio of gratings pattern.

Abstract: A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

Abstract: A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then formed on the LPCs. Thereafter, a plurality of second contacts is formed on a first portions of the first contacts and a plurality of bit lines connecting a second portions of the first contacts is formed, simultaneously. An inter-layer dielectric (ILD) layer is formed on the substrate to cover the second contacts and the bit lines. Subsequently, a plurality of capacitors is formed in the ILD layer. Thus, the fabrication of the capacitor is simplified.