Abstract: The present disclosure provides in some embodiments a thin film transistor, a display substrate, a display device and manufacturing methods thereof. The method for manufacturing the thin film transistor includes: forming an active layer having a first groove structure and a second groove structure, the first groove structure and the second groove structure being separated from each other; and depositing a conductive layer into the first groove structure and the second groove structure to form a first electrode and a second electrode of the thin film transistor.

Abstract: A thin film transistor, a method for manufacturing the same, an array substrate and a display device are provided. The method for manufacturing a thin film transistor includes: providing a substrate; forming an active layer and a light shielding layer covering the active layer on the substrate by a patterning process, the light shielding layer being formed of a photoresist material; and forming a source-drain electrode layer and a passivation layer covering the source-drain electrode layer.

Abstract: Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Abstract: The present disclosure provides a poly-silicon TFT, its manufacturing method, an array substrate and its manufacturing method. The method for manufacturing the poly-silicon TFT includes a step of, subsequent to the formation of an amorphous-silicon active layer and a source electrode of the TFT, applying an electrical signal to the source electrode, so as to maintain the source electrode at a predetermined temperature for a predetermined time period, thereby to crystallize the amorphous active layer into a poly-silicon active layer due to heat generated by the source electrode and transferred to the amorphous active layer.

Abstract: Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network.

Abstract: A source-drain structure is disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, a plurality of impurity ions in the drain-substrate junction and a plurality of impurity ions in the lightly-doped ultra-shallow junction are opposite-conductivity type ions. The drain-substrate junction can smooth out the steep surface of the lightly-doped ultra-shallow junction to minimize the maximum electric field and reduce the ion flow close to the channel, and effectively reduce the inter-band tunneling hot electron effect.

Abstract: A metal complex having a structural formula as follows, wherein, the metal atom M is selected from the group consisting of iridium (Ir), platinum (Pt), osmium (Os), rhenium (Re), ruthenium (Ru) and copper (Cu); R1, R2, R3 and R4 are independently selected from the group consisting of —F, —CF3, —CH3 and substituted phenyl; in the (C^N) substructure located on a left side of the metal atom M in the structural formula (I), C is located in a first aromatic or heteroaromatic ring, and N is located in a second heteroaromatic ring. The metal complex can be used in luminescent material of display devices.

Abstract: A touch screen, a fabrication method thereof and a display device are provided. The method comprises: forming a touch electrode (2) on a light emission side of a display panel (1) after the display panel is formed; and forming an organic transparent insulation layer (5) on the light emission side of the display panel (1) where the touch electrode (2) has been formed by using a coating process. An absolute value of a difference between a refractive index of the organic transparent insulation layer (5) and a refractive index of the touch electrode (2) is less than or equal to a predetermined value. Therefore, a problem of poor shadow elimination and a problem of white stripes in the touch screen are decreased without using a shadow elimination glass, a problem that the touch screen is damaged by high-temperature is avoided, and moreover, a formation apparatus for the touch electrode is prevented from being polluted by the organic transparent insulation layer.

Abstract: A source-drain structure and method of manufacturing the same are disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, a plurality of impurity ions in the drain-substrate junction and a plurality of impurity ions in the lightly-doped ultra-shallow junction are opposite-conductivity type ions. The drain-substrate junction can smooth out the steep surface of the lightly-doped ultra-shallow junction to minimize the maximum electric field and reduce the ion flow close to the channel, and effectively reduce the inter-band tunneling hot electron effect.

Abstract: A metal complex having a structural formula as follows, wherein, the metal atom M is selected from the group consisting of iridium (Ir), platinum (Pt), osmium (Os), rhenium (Re), ruthenium (Ru) and copper (Cu); R1, R2, R3 and R4 are independently selected from the group consisting of —F, —CF3, —CH3 and substituted phenyl; in the (C?N) substructure located on a left side of the metal atom M in the structural formula (I), C is located in a first aromatic or heteroaromatic ring, and N is located in a second heteroaromatic ring. The metal complex can be used in luminescent material of display devices.

Abstract: The present disclosure provides a poly-silicon TFT, its manufacturing method, an array substrate and its manufacturing method. The method for manufacturing the poly-silicon TFT includes a step of, subsequent to the formation of an amorphous-silicon active layer and a source electrode of the TFT, applying an electrical signal to the source electrode, so as to maintain the source electrode at a predetermined temperature for a predetermined time period, thereby to crystallize the amorphous active layer into a poly-silicon active layer due to heat generated by the source electrode and transferred to the amorphous active layer.

Abstract: A source-drain structure and method of manufacturing the same are disclosed. The source-drain structure includes a substrate containing a drain region and a source region. The drain region includes a lightly-doped ultra-shallow junction and a heavily-doped region, and a drain-substrate junction disposed in the vicinity of a junction between a side portion and a bottom portion of the lightly-doped ultra-shallow junction and the substrate, a plurality of impurity ions in the drain-substrate junction and a plurality of impurity ions in the lightly-doped ultra-shallow junction are opposite-conductivity type ions. The drain-substrate junction can smooth out the steep surface of the lightly-doped ultra-shallow junction to minimize the maximum electric field and reduce the ion flow close to the channel, and effectively reduce the inter-band tunneling hot electron effect.

Abstract: Systems and methods for implementing boundary-less hierarchical networks including methods of generating such networks in accordance with embodiments of the invention are disclosed. In one embodiment, a hierarchical network in an integrated circuit that includes a plurality of computing elements, where the plurality of computing elements have M outputs and N inputs, and a plurality of switches arranged into stages of switches wherein the plurality of computing elements are connected to switches in a first stage, the switches in the first stage are connected to the plurality of computing elements and switches in a second stage, where the switches in the second stage are connected to the switches in the first stage, at least M+1 adjacent computing elements can connect to at least two nearest neighboring computing elements via a stage 1 switch, and every computing element can connect with every other computing element within the hierarchical network.

Abstract: Systems and methods for power gating in logic and/or computing circuitry in accordance with embodiments of the inventions are disclosed. In one embodiment, a multiplexer for fine-grain power gating includes a first supply voltage and a second supply voltage, a plurality of inputs, a plurality of selection inputs, a selection circuitry configured to select one of the plurality of inputs, where one of the plurality of inputs is the first supply voltage and one of the selection inputs is a power gating enable input, an output inverter stage including a PMOS transistor and an NMOS transistor, where at least one input to the inverter stage is provided to the gates of the PMOS and NMOS transistors and selection of the power gating enable signal applies the first supply voltage to the gate of the PMOS transistor and places the PMOS transistor in a cutoff mode of operation.

Abstract: A cable for conveying an electrical submersible pump into and out of a well bore includes at least one strength member made of a composite material comprising a fiber reinforced plastic. A plurality of electrical conductors forming circumferential segments is disposed externally to the at least one strength member. A protective jacket encapsulates the at least one strength member and the plurality of electrical conductors.