Abstract: A directory processing method and apparatus are provided to resolve a problem that a directory occupies a relatively large quantity of caches in an existing directory processing solution. The method includes: receiving, by a first data node, a first request sent by a second data node; searching for, by the first data node, a matched directory entry in a directory of the first data node based on tag information and index information in a first physical address; creating, when no matched directory entry is found, a first directory entry of the directory based on the first request, where the first directory entry includes the tag information, first indication information, first pointer information, and first status information, the first pointer information is used to indicate that data in the memory address corresponding to the indication bit that is set to valid is read by the second data node.

Abstract: A directory processing method and apparatus are provided to resolve a problem that a directory occupies a relatively large quantity of caches in an existing directory processing solution. The method includes: receiving, by a first data node, a first request sent by a second data node; searching for, by the first data node, a matched directory entry in a directory of the first data node based on tag information and index information in a first physical address; creating, when no matched directory entry is found, a first directory entry of the directory based on the first request, where the first directory entry includes the tag information, first indication information, first pointer information, and first status information, the first pointer information is used to indicate that data in the memory address corresponding to the indication bit that is set to valid is read by the second data node.

Abstract: A cache coherence management method, a node controller, and a multiprocessor system that includes a first table, a second table, a node controller, and at least two nodes, where the node controller determines, in the first table according to address information of data, a first entry, where the first entry includes a first field and a second field. The first field records an occupation status of the data, the second field indicates a node that occupies the data exclusively when the first field includes an exclusive state, and the node controller determines a second entry in the second table according to the address information of the data and the second field when the first field includes a shared state, where the second entry includes a third field, and the third field indicates nodes that share the data.

Abstract: The present invention discloses a switching apparatus, a switching apparatus group, a data transmission method, and a computer system, and pertains to the field of computer technologies. The switching apparatus includes: a selection circuit module, a SERDES module, and a scheduling module. The selection circuit module establishes at least (n?1) static links with each of n modes, and any two static links that are connected to the selection circuit module and that belong to different nodes are connected to each other. The SERDES module is disposed on a static link connected to the selection circuit module. The scheduling module establishes connections to the selection circuit module and each of the n nodes. The selection circuit module further establishes at least one dynamic link with each of the n nodes.

Abstract: A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Abstract: A packet transmission method, packet transmission apparatus, and an interconnect interface are presented, where the method includes determining, by a sending node, whether an unrecoverable failure occurs in an active link, and if an unrecoverable failure occurs in the active link, selecting, from multiple communication links, at least one standby link except the active link to send a packet to a receiving node, so that the receiving node sends the packet to a receive end of the active link. In the method, for two nodes in an interconnect system that communicate with each other using multiple Links, when it is determined that an unrecoverable failure occurs in some of the Links, packets in retransmission buffers of transmit ends of the links in which the failure is unrecoverable are sent to a standby link.

Abstract: A cache coherence management method, a node controller, and a multiprocessor system that includes a first table, a second table, a node controller, and at least two nodes, where the node controller determines, in the first table according to address information of data, a first entry, where the first entry includes a first field and a second field. The first field records an occupation status of the data, the second field indicates a node that occupies the data exclusively when the first field includes an exclusive state, and the node controller determines a second entry in the second table according to the address information of the data and the second field when the first field includes a shared state, where the second entry includes a third field, and the third field indicates nodes that share the data.

Abstract: A directory maintenance method and apparatus are provided. The method includes sending, by a main memory according to a correspondence between a cache line in a directory and a cache, listening information to each cache corresponding to a cache line at a preset frequency; receiving, by each cache corresponding to the cache line, the listening information, and sending a listening response according to the listening information; and receiving, by the main memory, the listening response, and updating the directory according to the listening response, where the listening response includes a state of the cache line in the cache sending the listening response. The directory maintenance method and apparatus that are disclosed in the present invention can lower an impact of listening caused due to replacement on normal processing of a processor, and reduce degradation of system performance.

Abstract: The present disclosure provides a data read method and apparatus. An example method includes receiving a first read request message sent by a second processor at a first processor. If an address of the first data is within a range from an upper bound to a lower bound recorded in a first directory range register of the first processor, the first processor sends a first snoop message to at least one third processor other than the second processor, and simultaneously sends a second read request message to the memory. A first snoop response message sent by each of the at least one third processor according to the first snoop message is received. The first data sent by the memory according to the second data read request message is also received. The first processor sends the first data to the second processor according to the first snoop response message.

Abstract: The present invention disclose a memory access method, including: receiving, by a first processing module, a read request sent by a second processing module for caching; determining, according to a destination directory, one or more target storage spaces in which the target data is cached; sending a listening request to one or more target processing modules, so that the target processing module returns a listening response to the second processing module, where the listening response is used for responding to the expected status; returning a target packet to the second processing module, where the target packet includes the target data and a listening quantity; when a quantity of the listening response received by the second processing module matches the listening quantity, receiving an update packet sent by the second processing module; and updating the destination directory according to the update packet.

Abstract: A computer subsystem and a computer system, where the computer subsystem includes L composite nodes (CNs), each CN includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller (NC). Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the NC in the basic node. The NC in each basic node has a routing function. Any two NCs in the M basic nodes are interconnected. A connection between the L CNs formed through connections between NCs enables communication between any two NCs to be no more than three hops. Hence, the computer subsystem and the computer system can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Abstract: The present invention discloses a switching apparatus, a switching apparatus group, a data transmission method, and a computer system, and pertains to the field of computer technologies. The switching apparatus includes: a selection circuit module, a SERDES module, and a scheduling module. The selection circuit module establishes at least (n?1) static links with each of n modes, and any two static links that are connected to the selection circuit module and that belong to different nodes are connected to each other. The SERDES module is disposed on a static link connected to the selection circuit module. The scheduling module establishes connections to the selection circuit module and each of the n nodes. The selection circuit module further establishes at least one dynamic link with each of the n nodes.

Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Abstract: The present invention provide a directory management method including: receiving, by a first NC, a first data access request sent by a first processor on a local node; if the first NC determines that a first directory does not include a directory entry corresponding to a first access address and the first directory does not include an idle directory entry, clearing, by the first NC, directory content of a directory entry from the first directory; writing, by the first NC, directory content corresponding to the first data access request to the cleared directory entry; and if the first NC determines that a first snoop request is received, sending, by the first NC, a first snoop message to the processor on the local node.

Abstract: A method for temporarily storing data and a storage device is provided. The method for temporarily storing data is applied to the storage device, and the storage device includes a source agent and a target agent. The method includes: sending, by the source agent, a data obtaining request to the target agent; receiving, by the source agent, target data that is corresponding to the data obtaining request and is returned by the target agent; determining, by the source agent, whether a snooping request that is for the target data and sent by the target agent is received after the data obtaining request is sent and before the target data is received, where the snooping request indicates that the target agent is simultaneously processing an obtaining request from another source agent for the target data; and if the snooping request is received, discarding, by the source agent, the target data.

Abstract: A packet transmission method, packet transmission apparatus, and an interconnect interface are presented, where the method includes determining, by a sending node, whether an unrecoverable failure occurs in an active link, and if an unrecoverable failure occurs in the active link, selecting, from multiple communication links, at least one standby link except the active link to send a packet to a receiving node, so that the receiving node sends the packet to a receive end of the active link. In the method, for two nodes in an interconnect system that communicate with each other using multiple Links, when it is determined that an unrecoverable failure occurs in some of the Links, packets in retransmission buffers of transmit ends of the links in which the failure is unrecoverable are sent to a standby link.

Abstract: A network node comprises a receiver configured to receive a first packet, a processor coupled to the receiver and configured to process the first packet, and prioritize the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and a transmitter coupled to the processor and configured to transmit the first packet. An apparatus comprises a processor coupled to the memory and configured to generate instructions for a packet prioritization scheme, wherein the scheme assigns priority to packet transactions based on closeness to completion, and a memory coupled to the processor and configured to store the instructions. A method comprises receiving a first packet, processing the first packet, prioritizing the first packet according to a scheme, wherein the scheme assigns priority to packets based on phase, and transmitting the first packet.

Abstract: A method and an apparatus for processing a system command during memory backup. The method includes: acquiring a write address corresponding to a write operation command; if data corresponding to the write address has been read from a raw memory area but is not written to a backup memory area, mapping the write operation command to the raw memory area, and writing data to the write address in the raw memory area according to the write operation command; and deducting a set value from the write address to obtain an initial address to subsequently read data from the raw memory area. According to the embodiments of the present invention, a problem of system command blocking is solved during a memory backup operation, so that a system command is processed in a timely manner.

Abstract: The present invention provides a computer subsystem and a computer system. The computer subsystem includes L composite nodes, each composite node includes M basic nodes, each basic node includes N central processing units (CPUs) and one node controller. Any two CPUs in each basic node are interconnected. Each CPU in each basic node is connected to the node controller in the basic node. The node controller in each basic node has a routing function. Any two node controllers in the M basic nodes are interconnected. A connection between the L composite nodes formed through connections between node controllers enables communication between any two node controllers to be no more than three hops. The computer subsystem and the computer system according to embodiments of the present invention can reduce the kinds and the number of interconnection chips, and simplify an interconnection structure of a system, thereby improving reliability of the system.

Abstract: Embodiments of the present invention disclose a data processing method and apparatus. The method includes: first receiving an operation command, then searching, according to a memory address, a Cache memory in a Cache controller for data to be operated, and storing the operation command in a missed command buffer area in the Cache controller when the data to be operated is not found through searching in the Cache memory; then, storing data sent by an external memory in a data buffer area of the Cache controller after sending a read command to the external memory, and finally processing, according to a missed command, the data acquired from the external memory and the data carried in the missed command. The present invention applies to the field of computer systems.