Patents by Inventor Cheng-Kang Hu
Cheng-Kang Hu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11954841Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.Type: GrantFiled: June 3, 2022Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Lieh Chen, Cheng-Kang Hu, Cheng-Lung Wu, Jiun-Rong Pai
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Patent number: 11929271Abstract: An apparatus for inspecting wafer carriers is disclosed. In one example, the apparatus includes: a housing; a load port; a robot arm inside the housing; and a processor. The load port is configured to load a wafer carrier into the housing. The robot arm is configured to move a first camera connected to the robot arm. The first camera is configured to capture a plurality of images of the wafer carrier. The processor is configured to process the plurality of images to inspect the wafer carrier.Type: GrantFiled: July 13, 2020Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Shou-Wen Kuo, Sheng-Hsiang Chuang, Jiun-Rong Pai, Hsu-Shui Liu
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Patent number: 11915958Abstract: An apparatus and an operating method for automated wafer carrier handling are provided. The operation method includes bring a base frame and an engaging mechanism of an automated wafer carrier handling apparatus into abutting contact with a top flange mounted on a wafer carrier to limit at least one degree of freedom of movement of the top flange, where the engaging mechanism is disposed on the base frame; transporting the wafer carrier to a destination location by the automated wafer carrier handling apparatus; and releasing the top flange mounted on the wafer carrier from the automated wafer carrier handling apparatus at the destination location.Type: GrantFiled: March 25, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ren-Hau Wu, Cheng-Lung Wu, Jiun-Rong Pai, Cheng-Kang Hu
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Publication number: 20230384776Abstract: A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.Type: ApplicationFiled: July 31, 2023Publication date: November 30, 2023Inventors: Yung-Yao LEE, Cheng-Kang HU, Jui-Chun PENG, Hsu-Shui LIU
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Publication number: 20230326776Abstract: A cart for wafer transportation includes a cart body, a separator disposed between first and second wafer holders, an airtight lock configured to seal the cart body. A wafer transfer system includes a cart including a space for holding a wafer holder, a first workstation configured to load the wafer holder into the space and pressurize the space, and a second workstation configured to depressurize the space and unload the wafer holder from the space, wherein the cart is transportable between the first workstation and the second workstation. A method for transporting wafers includes docking a cart in a workstation; loading a wafer holder into a space of the cart; pressurizing the space to cause a pressure of the space to be greater than an atmospheric pressure; maintaining the pressure of the space at the pressure; and moving the cart carrying the wafer holder away from the workstation.Type: ApplicationFiled: August 24, 2022Publication date: October 12, 2023Inventors: Ren-Hau Wu, Cheng-Kang Hu, Chieh-Chun Lin, Jia-Hong Liao, Cheng-Yi Liu
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Patent number: 11768484Abstract: A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.Type: GrantFiled: March 31, 2021Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Yao Lee, Cheng-Kang Hu, Jui-Chun Peng, Hsu-Shui Liu
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Publication number: 20230282494Abstract: An apparatus and method for debonding a pair of bonded wafers are disclosed herein. In some embodiments, the debonding apparatus, comprises: a wafer chuck having a preset maximum lateral dimension and configured to rotate the pair of bonded wafers attached to a top surface of the wafer chuck, a pair of circular plate separating blades including a first separating blade and a second separating blade arranged diametrically opposite to each other at edges of the pair of bonded wafers, wherein the first and the second separating blades are inserted between a first and a second wafers of the pair of bonded wafers, and at least two pulling heads configured to pull the second wafer upwardly so as to debond the second wafer from the first wafer.Type: ApplicationFiled: May 15, 2023Publication date: September 7, 2023Inventors: Cheng-Fei YU, Chang-Chen Tsao, Ting-Yau Shiu, Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai
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Publication number: 20230207359Abstract: A load port receives a wafer carrier. An equipment front end module (EFEM) transfers semiconductor wafers to and from the wafer carrier via an access opening of a housing of the EFEM, and also transfers wafers to and from a semiconductor processing or characterization tool. A gas flow device disposed inside the housing of the EFEM is connected to receive a low humidity gas having relative humidity of 10% or less, and is positioned to flow the received low humidity gas across the access opening. A saturated pressure layer of the gas flow device has a permeability for the low humidity gas that increases with increasing distance from a gas inlet edge of the saturated pressure layer, for example due to holes of varying diameter and/or density passing through the saturated pressure layer. A filter layer of the gas flow device uniformizes the gas exiting the saturated pressure layer.Type: ApplicationFiled: February 24, 2022Publication date: June 29, 2023Inventors: Ren-Hau Wu, Cheng-Kang Hu, Yi-Fam Shiu, Cheng-Lung Wu, Hsu-Shui Liu
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Patent number: 11670524Abstract: An apparatus and method for debonding a pair of bonded wafers are disclosed herein. In some embodiments, the debonding apparatus, comprises: a wafer chuck having a preset maximum lateral dimension and configured to rotate the pair of bonded wafers attached to a top surface of the wafer chuck, a pair of circular plate separating blades including a first separating blade and a second separating blade arranged diametrically opposite to each other at edges of the pair of bonded wafers, wherein the first and the second separating blades are inserted between a first and a second wafers of the pair of bonded wafers, and at least two pulling heads configured to pull the second wafer upwardly so as to debond the second wafer from the first wafer.Type: GrantFiled: December 2, 2020Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Fei Yu, Chang-Chen Tsao, Ting-Yau Shiu, Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai
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Patent number: 11651981Abstract: A system and method for defect detection in a hole array on a substrate is disclosed herein. In one embodiment, a method for defect detection in a hole array on a substrate, includes: scanning a substrate surface using at least one optical detector, generating at least one image of the substrate surface; and analyzing the at least one image to detect defects in the hole array on the substrate surface based on a set of predetermined criteria.Type: GrantFiled: August 18, 2020Date of Patent: May 16, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jiao-Rou Liao, Sheng-Hsiang Chuang, Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Publication number: 20220317668Abstract: A cooling controller receives, from one or more sensors, wafer information associated with a wafer. The cooling controller determines a pattern mask area for the wafer based on the wafer information. The cooling controller determines a cooling time for the wafer based on the pattern mask area. The cooling controller causes a cooling plate to cool the wafer for a time duration equal to the cooling time. Determining the cooling time for a wafer based on a pattern mask area provides stable and consistent wafer temperatures for wafers having different mask and layout properties, which reduces mask overlay variation and increases wafer yield.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Yung-Yao LEE, Cheng-Kang HU, Jui-Chun PENG, Hsu-Shui LIU
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Publication number: 20220292667Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.Type: ApplicationFiled: June 3, 2022Publication date: September 15, 2022Inventors: Chih-Lieh CHEN, Cheng-Kang HU, Cheng-Lung WU, Jiun-Rong PAI
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Patent number: 11423526Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.Type: GrantFiled: November 13, 2020Date of Patent: August 23, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Lieh Chen, Cheng-Kang Hu, Cheng-Lung Wu, Jiun-Rong Pai
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Publication number: 20220261001Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.Type: ApplicationFiled: May 4, 2022Publication date: August 18, 2022Inventors: Cheng-Kang HU, Cheng-Hung CHEN, Yan-Han CHEN, Feng-Kuang WU, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
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Publication number: 20220216075Abstract: An apparatus and an operating method for automated wafer carrier handling are provided. The operation method includes bring a base frame and an engaging mechanism of an automated wafer carrier handling apparatus into abutting contact with a top flange mounted on a wafer carrier to limit at least one degree of freedom of movement of the top flange, where the engaging mechanism is disposed on the base frame; transporting the wafer carrier to a destination location by the automated wafer carrier handling apparatus; and releasing the top flange mounted on the wafer carrier from the automated wafer carrier handling apparatus at the destination location.Type: ApplicationFiled: March 25, 2022Publication date: July 7, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ren-Hau Wu, Cheng-Lung Wu, Jiun-Rong Pai, Cheng-Kang Hu
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Publication number: 20220156911Abstract: An image analysis device may align an image to determine a position of a wafer within the image. The wafer may include a plurality of wafer bumps. The image analysis device may mask, based on the position of the wafer, the image to obtain an image of a portion of the wafer. The image analysis device may binarize the image of the portion of the wafer to create a binarized image of the portion of the wafer. The image analysis device may determine a bump pattern, associated with the plurality of wafer bumps, based on the binarized image of the portion of the wafer. The image analysis device may perform a defect analysis of the determined bump pattern. The defect analysis may be associated with detecting regions of the portion of the wafer in which one or more wafer bumps have abnormal bump heights.Type: ApplicationFiled: November 13, 2020Publication date: May 19, 2022Inventors: Chih-Lieh CHEN, Cheng-Kang HU, Cheng-Lung WU, Jiun-Rong PAI
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Patent number: 11334080Abstract: In an embodiment a system includes: an automated vehicle configured to traverse a first predetermined path; and a sensor system located on the automated vehicle, the sensor system configured to detect a vertical obstacle along the first predetermined path along one or two floorboards ahead of the automated vehicle, wherein the automated vehicle is configured to traverse a second predetermined path in response to detecting the vertical obstacle.Type: GrantFiled: September 24, 2019Date of Patent: May 17, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Cheng-Hung Chen, Yan-Han Chen, Feng-Kuang Wu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo
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Patent number: 11295973Abstract: An apparatus and an operating method for automated wafer carrier handling are provided. The apparatus includes a base frame and an engaging mechanism disposed on the base frame. The engaging mechanism includes a controller and an active expansion component moveably coupled to the base frame and controlled by the controller to perform a reciprocating movement relative to the base frame. The active expansion component is driven by the controller to pass through the base frame to be engaged with a top flange mounted on the wafer carrier.Type: GrantFiled: February 11, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ren-Hau Wu, Cheng-Lung Wu, Jiun-Rong Pai, Cheng-Kang Hu
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Publication number: 20220059376Abstract: A system and method for defect detection in a hole array on a substrate is disclosed herein. In one embodiment, a method for defect detection in a hole array on a substrate, includes: scanning a substrate surface using at least one optical detector, generating at least one image of the substrate surface; and analyzing the at least one image to detect defects in the hole array on the substrate surface based on a set of predetermined criteria.Type: ApplicationFiled: August 18, 2020Publication date: February 24, 2022Inventors: Becky LIAO, Sheng-Hsiang CHUANG, Cheng-Kang HU, Hsu-Shui LIU, Jiun-Rong PAI, Shou-Wen KUO
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Patent number: 11152238Abstract: In an embodiment, a system includes a profiler configured to detect variations along a surface of a semiconductor stage; and a jig configured to move the profiler along an axis over the semiconductor stage.Type: GrantFiled: November 27, 2018Date of Patent: October 19, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Kang Hu, Hsu-Shui Liu, Jiun-Rong Pai, Shou-Wen Kuo, Sheng-Hsiang Chuang, Cheng-Hung Chen