Abstract: Disclosed are a method and a system for implementing synchronous parallel transmission over multiple channels. The method comprises: a sending end and a receiving end accessing an NoC through a sending port and a receiving port on the NoC, the sending port and the receiving port having a capability of simultaneously and parallelly transmitting data; the sending end sending data to the sending port of the NoC, and the sending port encoding the received data into a bipolar data symbol and modulating the bipolar data symbol by using a Walsh code; then the NoC synchronously adding and combining modulated symbols of all sending ports, and sending a signal after the combination to each receiving port through an NoC bus synchronously and parallelly; and the receiving port demodulating the received combined data according to the Walsh code thereof to obtain the bipolar data symbol, and then decoding the bipolar data symbol and sending the decoded bipolar data symbol to the receiving end.

Abstract: The disclosure provides a device with a capability of processing a Fast Fourier Transform Algorithm (FFT) radix 2 butterfly operation and an operation method thereof, the device at least includes a latch, a complex multiplier, a complex adder-subtractor, a switch and a complex conjugate Arithmetic Logical Unit (ALU). The complex operation unit of the disclosure has a simple structure. The parallel processing array composed of the complex operation unit has the capability of efficiently processing vectors and the FFT operation.

Abstract: The present disclosure provides a method and an apparatus for processing baseband uplink and downlink sub-frames. The method is for serial processing of uplink sub-frames and downlink sub-frames at a base station side of an LTE-TDD system, wherein a length of time slots for processing each sub-frame meets formulae ? { 3 ? ? x + 2 ? ? y + T L ? ? 2 ? 5.0 ? ? ms 2 ? ? x + y ? 4 - 2 ? ? T a - T d . By serial processing of the uplink and downlink sub-frames according to the present invention, more abundant processing time may be obtained. In other words, the baseband processor can operate at a lower speed, thus reducing an idle rate of the baseband processor and improving a resource utilization of the processor.

Abstract: Disclosed are a method and a system for implementing synchronous parallel transmission over multiple channels. The method comprises: a sending end and a receiving end accessing an NoC through a sending port and a receiving port on the NoC, the sending port and the receiving port having a capability of simultaneously and parallely transmitting data; the sending end sending data to the sending port of the NoC, and the sending port encoding the received data into a bipolar data symbol and modulating the bipolar data symbol by using a Walsh code; then the NoC synchronously adding and combining modulated symbols of all sending ports, and sending a signal after the combination to each receiving port through an NoC bus synchronously and parallely; and the receiving port demodulating the received combined data according to the Walsh code thereof to obtain the bipolar data symbol, and then decoding the bipolar data symbol and sending the decoded bipolar data symbol to the receiving end.

Abstract: The disclosure provides a device with a capability of processing a Fast Fourier Transform Algorithm (FFT) radix 2 butterfly operation and an operation method thereof, the device at least includes a latch, a complex multiplier, a complex adder-subtractor, a switch and a complex conjugate Arithmetic Logical Unit (ALU). The complex operation unit of the disclosure has a simple structure. The parallel processing array composed of the complex operation unit has the capability of efficiently processing vectors and the FFT operation.

Abstract: The present disclosure provides a method and an apparatus for processing baseband uplink and downlink sub-frames. The method is for serial processing of uplink sub-frames and downlink sub-frames at a base station side of an LTE-TDD system, wherein a length of time slots for processing each sub-frame meets formulae ? { 3 ? ? x + 2 ? ? y + T L ? ? 2 ? 5.0 ? ? ms 2 ? ? x + y ? 4 - 2 ? ? T a - T d . By serial processing of the uplink and downlink sub-frames according to the present invention, more abundant processing time may be obtained. In other words, the baseband processor can operate at a lower speed, thus reducing an idle rate of the baseband processor and improving a resource utilization of the processor.