Patents by Inventor Chengwei ZHENG

Chengwei ZHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11907329
    Abstract: A convolution calculation apparatus applied for convolution calculation of a convolution layer includes a decompression circuit, a data combination circuit and a calculation circuit. The decompression circuit decompresses compressed weighting data of a convolution kernel of the convolution layer to generate decompressed weighting data. The data combination circuit combines the decompressed weighting data and non-compressed data of the convolution kernel to restore a data order of weighting data of the convolution kernel. The calculation circuit performs calculation according to the weighting data of the convolution kernel and input data of the convolution layer.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: February 20, 2024
    Assignee: SIGMASTAR TECHNOLOGY LTD.
    Inventors: Fabo Bao, Donghao Liu, Wei Zhu, Chengwei Zheng
  • Patent number: 11886832
    Abstract: An operation device includes a quantizer circuit, a buffer circuit, a convolution core circuit and a multiply-add circuit. The quantizer circuit receives first feature data and performs asymmetric uniform quantization on the first feature data to obtain and store in the buffer circuit second feature data. The quantizer circuit further receives a first weighting coefficient and performs symmetric uniform quantization on the first weighting coefficient to obtain and store in the buffer circuit a second weight coefficient. The convolution core circuit performs a convolution operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 30, 2024
    Assignee: SIGMASTAR TECHNOLOGY LTD.
    Inventors: Xiaofeng Li, Chengwei Zheng, Bo Lin
  • Publication number: 20220092151
    Abstract: A convolution calculation apparatus applied for convolution calculation of a convolution layer includes a decompression circuit, a data combination circuit and a calculation circuit. The decompression circuit decompresses compressed weighting data of a convolution kernel of the convolution layer to generate decompressed weighting data. The data combination circuit combines the decompressed weighting data and non-compressed data of the convolution kernel to restore a data order of weighting data of the convolution kernel. The calculation circuit performs calculation according to the weighting data of the convolution kernel and input data of the convolution layer.
    Type: Application
    Filed: May 24, 2021
    Publication date: March 24, 2022
    Inventors: Fabo BAO, Donghao LIU, Wei ZHU, Chengwei ZHENG
  • Publication number: 20220036162
    Abstract: A network model quantization method includes: acquiring a target floating-point network model that is to be model quantized; determining an asymmetric quantization interval corresponding to an input value of the target floating-point network model; determining a symmetric quantization interval corresponding to a weight value of the target floating-point network model; and performing fixed-point quantization on the input value of the target floating-point network model according to the asymmetric quantization interval, and performing the fixed-point quantization on the weight value of the target floating-point network model according to the symmetric quantization interval to obtain a fixed-point network model corresponding to the target floating-point network model.
    Type: Application
    Filed: January 27, 2021
    Publication date: February 3, 2022
    Inventors: Tao XU, Chengwei ZHENG, Xiaofeng LI, Bo LIN
  • Publication number: 20210224033
    Abstract: An operation device includes a quantizer circuit, a buffer circuit, a convolution core circuit and a multiply-add circuit. The quantizer circuit receives first feature data and performs asymmetric uniform quantization on the first feature data to obtain and store in the buffer circuit second feature data. The quantizer circuit further receives a first weighting coefficient and performs symmetric uniform quantization on the first weighting coefficient to obtain and store in the buffer circuit a second weight coefficient. The convolution core circuit performs a convolution operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result.
    Type: Application
    Filed: December 28, 2020
    Publication date: July 22, 2021
    Inventors: Xiaofeng LI, Chengwei ZHENG, Bo LIN