Patents by Inventor Cheng-Wen Yang
Cheng-Wen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11991838Abstract: An embedded circuit board made without gas bubbles or significant internal gaps according to a manufacturing method which is here disclosed comprises an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces, a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.Type: GrantFiled: March 31, 2022Date of Patent: May 21, 2024Assignees: QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD, Avary Holding (Shenzhen) Co., Limited.Inventors: Cheng-Yi Yang, Hao-Wen Zhong, Biao Li, Ming-Jaan Ho, Ning Hou
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Publication number: 20240162833Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
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Publication number: 20240160928Abstract: A method for enhancing kernel reparameterization of a non-linear machine learning model includes providing a predefined machine learning model, expanding a kernel of the predefined machine learning model with a non-linear network for convolution operation of the predefined machine learning model to generate the non-linear machine learning model, training the non-linear machine learning model, reparameterizing the non-linear network back to a kernel for convolution operation of the non-linear machine learning model to generate a reparameterized machine learning model, and deploying the reparameterized machine learning model to an edge device.Type: ApplicationFiled: November 10, 2023Publication date: May 16, 2024Applicant: MEDIATEK INC.Inventors: Po-Hsiang Yu, Hao Chen, Cheng-Yu Yang, Peng-Wen Chen
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Publication number: 20240160919Abstract: In aspects of the disclosure, a method, a system, and a computer-readable medium are provided. The method of building a kernel reparameterization for replacing a convolution-wise operation kernel in training of a neural network comprises selecting one or more blocks from tensor blocks and operations; and connecting the selected one or more blocks with the selected operations to build the kernel reparameterization. The kernel reparameterization has a dimension same as that of the convolution-wise operation kernel.Type: ApplicationFiled: October 17, 2023Publication date: May 16, 2024Inventors: Po-Hsiang Yu, Hao Chen, Peng-Wen Chen, Cheng-Yu Yang
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Publication number: 20240161013Abstract: A reparameterization method for initializing a machine learning model includes initializing a prefix layer of a first low dimensional layer in the machine learning model and a postfix layer of the first low dimensional layer, inverting the prefix layer to generate an inverse prefix layer of the first low dimensional layer, inverting the postfix layer to generate an inverse postfix layer of the first low dimensional layer, combining the inverse prefix layer, the first low dimensional layer and the inverse postfix layer to form a high dimensional layer, generating parallel operation layers from the high dimensional layer, and assigning initial weights to the parallel operation layers.Type: ApplicationFiled: November 3, 2023Publication date: May 16, 2024Applicant: MEDIATEK INC.Inventors: Cheng-Yu Yang, Hao Chen, Po-Hsiang Yu, Peng-Wen Chen
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Publication number: 20240152679Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.Type: ApplicationFiled: January 17, 2024Publication date: May 9, 2024Inventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
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Patent number: 11968869Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.Type: GrantFiled: April 28, 2022Date of Patent: April 23, 2024Assignee: InnoLux CorporationInventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
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Publication number: 20240130050Abstract: An embedded circuit board, made without gas bubbles or significant internal gaps according to a manufacturing method which is provided, includes an inner layer assembly, an embedded element, and first and second insulating elements. The inner layer assembly comprises a first main portion with opposing first and second surfaces and a first groove not extending to the second surface is positioned at the first surface. A first opening penetrates the second surface, and the first opening and the first groove are connected. The first groove carries electronic elements for embedment. The first insulating element covers the first surface and a surface of the embedded element away from the second surface. The second insulating element covers the second surface and extends into the first opening to be in contact with the embedded element.Type: ApplicationFiled: December 28, 2023Publication date: April 18, 2024Inventors: Cheng-Yi Yang, Hao-Wen Zhong, Biao Li, Ming-Jaan Ho, Ning Hou
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Publication number: 20240120317Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.Type: ApplicationFiled: July 13, 2023Publication date: April 11, 2024Applicant: Western Digital Technologies, Inc.Inventors: Cheng-Hsiung Yang, Chien Te Chen, Cong Zhang, Ching-Chuan Hsieh, Yu-Ying Tan, Juan Zhou, Ai-wen Wang, Yih-Fran Lee, Yu-Wen Huang
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Patent number: 11914941Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.Type: GrantFiled: April 19, 2021Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Rachid Salik, Chin-Chang Hsu, Cheng-Chi Wu, Chien-Wen Chen, Wen-Ju Yang
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Publication number: 20120144068Abstract: A data system includes an article such as footwear, model car or toy, an electronic module carried by said article, the electronic module having a microprocessor and a data storage device to which the user can selectively store and retrieve data, a data input to the electronic module configured for the user to input and store data on the data storage device, a controller in electronic communication with the electronic module for controlling data output, and an audio output device in electronic communication with the electronic module for receiving data output from the electronic module.Type: ApplicationFiled: January 17, 2012Publication date: June 7, 2012Inventors: Frank Lay, Cheng-Wen Yang, Lavetta Willis
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Patent number: 8103802Abstract: A data system includes an article such as footwear, model car or toy, an electronic module carried by said article, the electronic module having a microprocessor and a data storage device to which the user can selectively store and retrieve data, a data input to the electronic module configured for the user to input and store data on the data storage device, a controller in electronic communication with the electronic module for controlling data output, and an audio output device in electronic communication with the electronic module for receiving data output from the electronic module.Type: GrantFiled: January 17, 2008Date of Patent: January 24, 2012Assignee: LL International Shoe CompanyInventors: Frank Lay, Cheng-Wen Yang, Lavetta Willis
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Publication number: 20080167741Abstract: A data system includes an article such as footwear, model car or toy, an electronic module carried by said article, the electronic module having a microprocessor and a data storage device to which the user can selectively store and retrieve data, a data input to the electronic module configured for the user to input and store data on the data storage device, a controller in electronic communication with the electronic module for controlling data output, and an audio output device in electronic communication with the electronic module for receiving data output from the electronic module.Type: ApplicationFiled: January 17, 2008Publication date: July 10, 2008Inventors: Frank Lay, Cheng-Wen Yang, Lavetta Willis