Patents by Inventor Chengyan Liu

Chengyan Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package in package (PiP) electronic device and manufacturing method thereof
    Patent number: 9397068
    Abstract: A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: July 19, 2016
    Assignee: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Fei Qin, Guofeng Xia, Tong An, Wei Wu, Chengyan Liu, Wenhui Zhu
  • Package in Package (PiP) Electronic Device and Manufacturing Method thereof
    Publication number: 20150348934
    Abstract: A manufacturing method for Package in Package (PiP) electronic device based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating IC chip for wire bonding, adhesive material, metal wire, chip pad and a plurality of leads to form a multi-row QFN package as an inner package. Flip-chip bonding IC chip with solder bumps on the first metal material layer of leads. Encapsulating IC chip with solder bumps, the multi-row QFN package, adhesive material, and leads to form an array of PiP electronic devices. Sawing and separating the PiP electronic device array, forming PiP electronic device unit.
    Type: Application
    Filed: December 4, 2012
    Publication date: December 3, 2015
    Applicant: BEIJING UNIVERSITY OF TECHNOLOGY
    Inventors: Fei Qin, Guofeng Xia, Tong An, Wei Wu, Chengyan Liu, Wenhui Zhu
  • FCOC (Flip Chip On Chip) package and manufacturing method thereof
    Patent number: 8951840
    Abstract: A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: February 10, 2015
    Assignee: Beijing University of Technology
    Inventors: Fei Qin, Guofeng Xia, Tong An, Chengyan Liu, Wei Wu, Wenhui Zhu
  • FCoC (Flip Chip on Chip) Package and Manufacturing Method thereof
    Publication number: 20140302640
    Abstract: A manufacturing method for Flip Chip on Chip (FCoC) package based on multi-row Quad Flat No-lead (QFN) package is provided wherein the lower surface of plate metallic base material are half-etched to form grooves. Insulation filling material is filled in the half-etched grooves. The upper surface of plate metallic base material is half-etched to form chip pad and multi-row of leads. Encapsulating first IC chip, second IC chip, solder bumps, underfill material, and metal wire to form an array of FCoC package based on the type of multi-row QFN package. Sawing and separating the FCoC package array, and forming FCoC package unit.
    Type: Application
    Filed: December 4, 2012
    Publication date: October 9, 2014
    Inventors: Fei Qin, Guofeng Xia, Tong An, Chengyan Liu, Wei Wu, Wenhui Zhu