Patents by Inventor Chengyu Niu

Chengyu Niu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10553497
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: February 4, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Chengyu Niu, Heng Yang
  • Patent number: 10546789
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: January 28, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Chengyu Niu, Heng Yang
  • Patent number: 10438856
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: October 8, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: John H. Zhang, Chengyu Niu, Heng Yang
  • Patent number: 10283608
    Abstract: A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan Zhang, Frank Mont, Mark Raymond, Chengyu Niu
  • Publication number: 20180269297
    Abstract: A conductive source/drain contact is formed within a trench overlying a raised epitaxial source/drain junction. The conductive contact includes a conductive liner and a conductive fill material formed directly over the conductive liner. The conductive fill material is selected from a platinum group metal such as ruthenium. The conductive liner may be directionally deposited into the trench and is adapted to form a metal silicide in situ through a reaction with the epitaxial layer.
    Type: Application
    Filed: March 17, 2017
    Publication date: September 20, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Xunyuan ZHANG, Frank MONT, Mark RAYMOND, Chengyu NIU
  • Patent number: 10026693
    Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: July 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Mark V. Raymond, Praneet Adusumilli, Chengyu Niu
  • Publication number: 20170243823
    Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.
    Type: Application
    Filed: May 8, 2017
    Publication date: August 24, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Mark V. Raymond, Praneet Adusumilli, Chengyu Niu
  • Patent number: 9679807
    Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 13, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Mark V. Raymond, Praneet Adusumilli, Chengyu Niu
  • Publication number: 20170148669
    Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.
    Type: Application
    Filed: November 20, 2015
    Publication date: May 25, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Vimal Kamineni, Mark V. Raymond, Praneet Adusumilli, Chengyu Niu
  • Publication number: 20170011971
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Application
    Filed: September 26, 2016
    Publication date: January 12, 2017
    Inventors: John H. ZHANG, Chengyu NIU, Heng YANG
  • Publication number: 20160118307
    Abstract: Methods and devices for enhancing mobility of charge carriers. An integrated circuit may include semiconductor devices of two types. The first type of device may include a metallic gate and a channel strained in a first manner. The second type of device may include a metallic gate and a channel strained in a second manner. The gates may include, collectively, three or fewer metallic materials. The gates may share a same metallic material. A method of forming the semiconductor devices on an integrated circuit may include depositing first and second metallic layers in first and second regions of the integrated circuit corresponding to the first and second gates, respectively.
    Type: Application
    Filed: December 31, 2015
    Publication date: April 28, 2016
    Inventors: John H. Zhang, Chengyu Niu, Heng Yang
  • Patent number: 9111938
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: August 18, 2015
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES, INC., Renesas Electronics Corporation, STMICROELECTRONICS, INC.
    Inventors: Frieder H. Baumann, Tibor Bolom, Chao-Kun Hu, Koichi Motoyama, Chengyu Niu, Andrew H. Simon
  • Publication number: 20150061135
    Abstract: A structure having a diffusion barrier positioned adjacent to a sidewall and a bottom of an opening being etched in a layer of dielectric material. The structure also having a metal liner positioned directly on top of the diffusion barrier, a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper, a copper material positioned directly on top of the seed layer, a metallic cap positioned directly on top of and selective to the copper material, and a capping layer positioned directly on top of and adjacent to the metallic cap.
    Type: Application
    Filed: November 12, 2014
    Publication date: March 5, 2015
    Inventors: Frieder H. Baumann, Tibor Bolom, Chao-Kun Hu, Koichi Motoyama, Chengyu Niu, Andrew H. Simon
  • Publication number: 20140138837
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a sandwiched diffusion barrier and metal liner structure and a metal seed layer. The sandwiched diffusion barrier and metal liner structure includes a conformal metal liner layer sandwiched between a first diffusion barrier layer and a second diffusion barrier layer. The metal seed layer is at least lightly doped. The lined trench is then filled by electroplating with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicants: STMicroelectronics, Inc., GlobalFoundries Inc, International Business Machines Corporation
    Inventors: Chengyu Niu, Andrew Simon, Tibor Bolom
  • Publication number: 20140138832
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Application
    Filed: November 20, 2012
    Publication date: May 22, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Patent number: 8729702
    Abstract: A trench is opened in a dielectric layer. The trench is then lined with a barrier layer and a metal seed layer. The metal seed layer is non-uniformly doped and exhibits a vertical doping gradient varying as a function of trench depth. The lined trench is then filled with a metal fill material. A dielectric cap layer is then deposited over the metal filled trench. Dopant from the non-uniformly doped metal seed layer is then migrated to an interface between the metal filled trench and the dielectric cap layer to form a self-aligned metal cap.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: May 20, 2014
    Assignees: STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Chengyu Niu, Andrew Simon, Keith Kwong Hon Wong, Yun-Yu Wang
  • Patent number: 8493171
    Abstract: A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator to the trimmable resistor. The resistance of the trimmable resistor is permanently increased or decreased when the temperature of the resistor is increased to a value within a particular range of temperatures.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: July 23, 2013
    Assignees: STMicroelectronics, Inc., STMicroelectronics (Grenoble) SAS
    Inventors: Olivier Le Neel, Pascale Dumont-Girard, Chengyu Niu, Fuchao Wang, Michel Arnoux
  • Patent number: 8400257
    Abstract: The present disclosure is directed to a thin film resistor structure that includes a resistive element electrically connecting first conductor layers of adjacent interconnect structures. The resistive element is covered by a dielectric cap layer that acts as a stabilizer and heat sink for the resistive element. Each interconnect includes a second conductor layer over the first conductive layer. The thin film resistor includes a chromium silicon resistive element covered by a silicon nitride cap layer.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: March 19, 2013
    Assignees: STMicroelectronics PTE Ltd, STMicroelectronics, Inc.
    Inventors: Ting Fang Lim, Chengyu Niu, Olivier Le Neel, Calvin Leung
  • Publication number: 20120266452
    Abstract: A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator to the trimmable resistor. The resistance of the trimmable resistor is permanently increased or decreased when the temperature of the resistor is increased to a value within a particular range of temperatures.
    Type: Application
    Filed: July 3, 2012
    Publication date: October 25, 2012
    Applicants: STMicroelectronics (Grenoble) SAS, STMicroelectronics, Inc.
    Inventors: Olivier Le Neel, Pascale Dumont-Girard, Chengyu Niu, Fuchao Wang, Michel Arnoux
  • Patent number: 8242876
    Abstract: A trimmable resistor for use in an integrated circuit is trimmed using a heater. The heater is selectively coupled to a voltage source. The application of voltage to the heater causes the heater temperature to increase and produce heat. The heat permeates through a thermal separator to the trimmable resistor. The resistance of the trimmable resistor is permanently increased or decreased when the temperature of the resistor is increased to a value within a particular range of temperatures.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: August 14, 2012
    Assignees: STMicroelectronics, Inc., STMicroelectronics (Grenoble) SAS
    Inventors: Olivier Le Neel, Pascale Dumont-Girard, Chengyu Niu, Fuchao Wang, Michel Arnoux