Abstract: The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Abstract: Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics.

Abstract: The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Abstract: The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: Sensor circuitry including probabilistic switching devices, such as spin-transfer torque magnetic tunnel junctions (STT-MTJs), is configured to perform ultra-low power analog to digital conversion and compressive sensing. The analog to digital conversion and compressive sensing processes are performed simultaneously and in a manner that is native to the devices due to their probabilistic switching characteristics.

Abstract: A discrete time receiver includes a low noise transconductance amplifier (LNTA), a discrete time sampler, a passive discrete time circuit, and a switched capacitor amplifier. The LNTA amplifies a received RF signal and provides an amplified RF signal. The discrete time sampler samples the amplified RF signal (e.g., with multiple phases of a sampling clock) and provides first analog samples. The passive discrete time circuit decimates and filters the first analog samples and provides second analog samples. The switched capacitor amplifier amplifies the second analog samples and provides third analog samples. The discrete time receiver may further include a second passive discrete time circuit, a second switched capacitor amplifier, and an analog-to-digital converter (ADC) that digitizes baseband analog samples and provides digital samples. The discrete time receiver can flexibly support different system bandwidths and center frequencies.

Abstract: Multiple streams from multiple circuit paths are Block-TDM (Block-Time-Division-Multiplexing) aggregated into a single stream that passes via a single path through processing circuitry capable of handling the aggregated signal. The cost of providing redundant processing circuitry is avoided. After processing in the single path, the resulting signal is Block-TDM de-aggregated to generate multiple streams. Each output stream is substantially the same as if its corresponding input stream had been processed in a separate path using separate processing circuitry. The path-sharing technique is usable to pass multiple streams from multiple radio receivers through one superior Delta-Sigma ADC (DSADC) as opposed to using multiple flat ADCs to process information from the multiple receivers. In one example, the DSADC can be used because the aggregation is Block-TDM-based and the de-aggregator involves a digital low pass filter.

Abstract: Techniques for generating a differential output voltage between first and second output voltages that is double a differential input voltage between first and second input voltages. In one aspect, first and second capacitors of a constituent voltage doubler are charged to a differential input voltage during a charging phase. During an output phase non-overlapping in time with the charging phase, the first and second capacitors are stacked in series to generate the differential output voltage. The first and second capacitors are both coupled to a single common-mode voltage to provide a predefined common-mode output voltage. Further techniques for providing two or more constituent voltage doublers to extend the output phase are described.

Abstract: Multiple streams from multiple circuit paths are Block-TDM (Block-Time-Division-Multiplexing) aggregated into a single stream that passes via a single path through processing circuitry capable of handling the aggregated signal. The cost of providing redundant processing circuitry is avoided. After processing in the single path, the resulting signal is Block-TDM de-aggregated to generate multiple streams. Each output stream is substantially the same as if its corresponding input stream had been processed in a separate path using separate processing circuitry. The path-sharing technique is usable to pass multiple streams from multiple radio receivers through one superior Delta-Sigma ADC (DSADC) as opposed to using multiple flat ADCs to process information from the multiple receivers. In one example, the DSADC can be used because the aggregation is Block-TDM-based and the de-aggregator involves a digital low pass filter.

Abstract: Techniques for generating a differential output voltage between first and second output voltages that is double a differential input voltage between first and second input voltages. In one aspect, first and second capacitors of a constituent voltage doubler are charged to a differential input voltage during a charging phase. During an output phase non-overlapping in time with the charging phase, the first and second capacitors are stacked in series to generate the differential output voltage. The first and second capacitors are both coupled to a single common-mode voltage to provide a predefined common-mode output voltage. Further techniques for providing two or more constituent voltage doublers to extend the output phase are described.

Abstract: A passive switched-capacitor (PSC) filter includes (i) an array of capacitors that can store and share electrical charge and (ii) an array of switches that can couple the capacitors to a summing node. Each switch couples an associated capacitor to the summing node when enabled. Each capacitor stores a voltage value from the summing node when selected for charging and shares electrical charge with other capacitors via the summing node when selected for charge sharing. The PSC filter may include multiple sections for multiple filter taps. Each section includes one or more capacitors of equal size determined based on a corresponding filter coefficient. The capacitors in each section may be sequentially selected for charging with an input or output signal, one capacitor in each clock cycle. In each clock cycle, one capacitor in each section may be selected for charge sharing to generate the output signal.

Abstract: Passive switched-capacitor (PSC) filters are described herein. In one design, a PSC filter implements a second-order infinite impulse response (IIR) filter with two complex first-order IIR sections. Each complex first-order IIR section includes three sets of capacitors. A first set of capacitors receives a real input signal and an imaginary delayed signal, stores and shares electrical charges, and provides a real filtered signal. A second set of capacitors receives an imaginary input signal and a real delayed signal, stores and shares electrical charges, and provides an imaginary filtered signal. A third set of capacitors receives the real and imaginary filtered signals, stores and shares electrical charges, and provides the real and imaginary delayed signals. In another design, a PSC filter implements a finite impulse response (FIR) section and an IIR section for a complex first-order IIR section. The IIR section includes multiple complex filter sections operating in an interleaved manner.

Abstract: A discrete time receiver includes a low noise transconductance amplifier (LNTA), a discrete time sampler, a passive discrete time circuit, and a switched capacitor amplifier. The LNTA amplifies a received RF signal and provides an amplified RF signal. The discrete time sampler samples the amplified RF signal (e.g., with multiple phases of a sampling clock) and provides first analog samples. The passive discrete time circuit decimates and filters the first analog samples and provides second analog samples. The switched capacitor amplifier amplifies the second analog samples and provides third analog samples. The discrete time receiver may further include a second passive discrete time circuit, a second switched capacitor amplifier, and an analog-to-digital converter (ADC) that digitizes baseband analog samples and provides digital samples. The discrete time receiver can flexibly support different system bandwidths and center frequencies.

Abstract: The described apparatus and methods may include a receiver configured to receive a control signal, and a controller configured to regulate power consumption of the receiver during intervals of less than one radio frame based on the control signals. The controller may also be configured to regulate power consumption of a transmitter during intervals of less than one radio frame based on the control signal.

Abstract: One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.

Abstract: One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.

Abstract: One or more methods and systems are presented for performing gain and timing acquisition of data read from one or more data sectors of a hard disk drive. The gain and timing information may be used to synchronize a read channel receiver of the hard disk drive to the data read from the data sector(s). In a representative embodiment, the one or more methods comprises determining one or more frequency and phase offsets using one or more preambles of one or more data sectors residing in a hard disk drive. In a representative embodiment, the gain of the one or more preambles may be determined. In another representative embodiment, the one or more systems used to determine one or more phase and frequency offsets, and amplitudes, comprise hardware and/or software capable of utilizing a sequence of consecutive samples provided by one or more preambles of one or more data sectors.