Abstract: The present invention provides a current detection circuit applied to a SiC field effect transistor. The current detection circuit includes a current detection loop and an acquisition loop on the current detection loop. The current detection loop includes a voltage source, a capacitor, a first SiC field effect transistor, a second SiC field effect transistor, and a sampling resistor. The first SiC field effect transistor is connected to a power signal. The second SiC field effect transistor is connected to a pulse signal. The acquisition loop includes a compensating resistor and a compensating inductor. The compensating resistor and the compensating inductor are connected in series and then connected in parallel at two ends of the sampling resistor to counteract the influence of total parasitic inductance in the current detection loop.

Abstract: The present invention relates to a three-dimensional integrated package device for a high-voltage silicon carbide power module, comprising a source substrate, first chip submodules, a first driving terminal, a first driving substrate, a ceramic housing, a metal substrate, a water inlet, a water outlet, second chip submodules, a second driving terminal, a second driving substrate and a drain substrate from top to bottom; and each first chip submodule is composed of a driving connection substrate, a power source metal block, a first driving gate metal post, second driving gate metal posts, a silicon carbide bare chip, an insulation structure and the like. A three-dimensional integrated half-bridge structure is adopted to greatly reduce corresponding parasitic parameters.

Abstract: The present invention relates to a three-dimensional integrated package device for a high-voltage silicon carbide power module, comprising a source substrate, first chip submodules, a first driving terminal, a first driving substrate, a ceramic housing, a metal substrate, a water inlet, a water outlet, second chip submodules, a second driving terminal, a second driving substrate and a drain substrate from top to bottom; and each first chip submodule is composed of a driving connection substrate, a power source metal block, a first driving gate metal post, second driving gate metal posts, a silicon carbide bare chip, an insulation structure and the like. A three-dimensional integrated half-bridge structure is adopted to greatly reduce corresponding parasitic parameters.