Abstract: A method includes forming a composite material layer over a carrier, the composite material layer including particles of a filler material incorporated into a base material, forming a set of through vias over a first side of the composite material layer, attaching a die over the first side of the composite material layer, the die being spaced apart from the set of through vias, forming a molding material over the first side of the composite material layer, the molding material least laterally encapsulating the die and the through vias of the set of through vias, forming a redistribution structure over the die and the molding material, the redistribution structure electrically connected to the through vias, forming openings in a second side of the composite material layer opposite the first side, and forming conductive connectors in the openings, the conductive connectors electrically connected to the through vias.

Abstract: A method for forming a chip package structure is provided. The method includes providing an electrical substrate and a photonic substrate over and bonded to the electrical substrate. The method includes partially removing the dielectric structure to form a first through hole and a second through hole in the dielectric structure. The first through hole passes through the dielectric structure and exposes the first wiring layer. The method includes forming a first conductive via structure and a second conductive via structure in the first through hole and the second through hole respectively. The first conductive via structure is in direct contact with the first wiring layer, and the second conductive via structure is spaced apart from the first wiring layer.

Abstract: Optical devices and methods of manufacture are presented herein. In an embodiment, an apparatus is provided that includes a notch filter, an optical signal detector positioned adjacent to the notch filter, and a mirror positioned to adjacent to the notch filter.

Abstract: A semiconductor device includes a first Chip-On-Wafer (CoW) device having a first interposer and a first die attached to a first side of the first interposer; a second CoW device having a second interposer and a second die attached to a first side of the second interposer, the second interposer being laterally spaced apart from the first interposer; and a redistribution structure extending along a second side of the first interposer opposing the first side of the first interposer and extending along a second side of the second interposer opposing the first side of the second interposer, the redistribution structure extending continuously from the first CoW device to the second CoW device.

Abstract: A package includes a redistribution structure that includes conductive features and first waveguides; first dies and second dies attached to the redistribution structure, wherein the first dies are different than the second dies, wherein the first dies are electrically connected to respectively corresponding second dies through the redistribution structure; and optical bridge structures attached to the redistribution structure, wherein the optical bridge structures are optically coupled to the first waveguides, wherein the optical bridge structures are electrically connected to respectively corresponding first dies and respectively corresponding second dies through the redistribution structure.

Abstract: A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.

Abstract: A package structure and method for forming the same are provided. The package structure includes a top interposer formed over a substrate, and a first die formed over the top interposer. The first die includes an optical package structure, and the optical package structure includes first optical components. The first die also includes an electronic die bonded to the optical package structure to form a hybrid bonding structure. The hybrid bonding structure includes a metal-to-metal bonding and dielectric-to-dielectric bonding. The package structure includes an optical die adjacent to the first die, and the top interposer is shared by the optical die and the first die.

Abstract: A semiconductor device includes a redistribution structure, an integrated circuit package attached to a first side of the redistribution structure and a core substrate coupled to a second side of the redistribution structure with a first conductive connector and a second conductive connector. The second side is opposite the first side. The semiconductor device further includes a top layer of the core substrate including a dielectric material and a chip disposed between the redistribution structure and the core substrate. The chip is interposed between sidewalls of the dielectric material.

Abstract: A semiconductor device includes a first interconnect structure, a device layer, a second interconnect structure, a diamond layer, a passivation layer, and an electrical connector. The device layer is disposed over the first interconnect structure. The second interconnect structure is disposed over the device layer and comprises a topmost metallization pattern. The diamond layer is disposed over the second interconnect structure and at least revealing a part of the topmost metallization pattern. The passivation layer covers the diamond layer and reveals the part of the topmost metallization pattern. The electrical connector is disposed over the passivation layer and bonded to the part of the topmost metallization pattern.

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

Abstract: A semiconductor device structure and a formation method are provided. The method includes receiving a substrate, and the substrate has a dielectric layer and a semiconductor layer over the dielectric layer. The method also includes forming a p-type doped region and an n-type doped region in the semiconductor layer. The method further includes partially removing the semiconductor layer and the dielectric layer to form a recess exposing portions of the p-type doped region and the n-type doped region. In addition, the method includes forming a photo-sensing structure over sidewalls of the recess, and the photo-sensing structure is spaced apart from a bottom of the recess.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a p-type doped structure and an n-type doped structure. The method also includes forming a photo-sensing structure, and a portion of the photo-sensing structure is between the p-type doped structure and the n-type doped structure. The method further includes forming a semiconductor cap over the photo-sensing structure. The semiconductor cap is p-type doped.

Abstract: A photonic device and a manufacturing method thereof are provided. The photonic device includes an oxide layer, a first waveguide structure and a semiconductor-insulator-capacitor modulator. The oxide layer has a first surface and a second surface opposite to the first surface. The first waveguide structure is formed on the first surface of the oxide layer. The semiconductor-insulator-capacitor modulator is formed on the second surface of the oxide layer. The semiconductor-insulator-capacitor modulator includes a first terminal, a second terminal and a capacitor dielectric layer. The first terminal is optically connected with the first waveguide structure. The capacitor dielectric layer is disposed between the first terminal and the second terminal.

Abstract: Optical devices and methods of manufacture are presented in which optical interposers are embedded within interposers. In some embodiments a method includes embedding an optical interposer into an interposer with one or more waveguides, with or without other semiconductor devices, and then bonding one or more semiconductor devices onto the interposer.

Abstract: In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: A fiber array unit includes a support structure, a base on the support structure including an outer base layer, and an inner base layer attached to the outer base layer and including a recess having a recess bottom and a recess sidewall adjoining the recess bottom. The recess may be located at an interface between the outer base layer and the inner base layer and the interface may be substantially perpendicular to the support structure. The fiber array unit also includes a mirror including a reflective layer on the recess bottom and recess sidewall.

Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a P-type region and an N-type region. The P-type region and the N-type region are spaced apart from each other. The semiconductor device structure includes a light absorption structure in the substrate between the P-type region and an N-type region. The semiconductor device structure includes a first P-type film between the light absorption structure and the P-type region. The semiconductor device structure includes a second P-type film between the light absorption structure and the N-type region, wherein a portion of the substrate separates the second P-type film from the N-type region.

Abstract: A method of forming a package assembly includes the following operations. At least one integrated circuit structure is bonded to an interposer structure. A photonic structure is bonded to the interposer structure aside the at least one integrated circuit structure. A glass substrate is assembled to a fiber array unit. The glass substrate with the fiber array unit is bonded to the photonic structure. A laser writing process is performed to the glass substrate, so as to form a laser written waveguide structure inside the glass substrate, wherein the laser written waveguide structure is optically coupled to the fiber array unit and the photonic structure.