Abstract: An example memory device includes: memory cells constituting memory cell rows coupled to word lines and memory strings coupled to bit lines; and a peripheral circuit configured to: perform a read operation on the memory cells connected to a first word line to obtain at least two read values; during the read operation performed on the memory cells connected to the first word line, divide the memory cells connected to a second word line into at least two groups based on threshold voltages of the memory cells connected to the second word line; and determine read results of the memory cells connected to the first word line from the at least two read values based on grouping information of the memory cells connected to the second word line. The first word line and the second word line are word lines adjacent to each other.

Abstract: In certain aspects, a memory device includes memory cells and a peripheral circuit coupled to the memory cells. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first and second word lines. The peripheral circuit is configured to program the target memory cell, perform a first sample read on the first memory cell to obtain a first sample value of the first memory cell, configure one or more verification parameters of the target memory cell based on the first sample value, perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell, and configure one or more read parameters of the target memory cell based on the second sample value.

Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

Abstract: The present disclosure provides a method of operating a memory, a memory, a memory system and an electronic device. In an example, a method of operating a memory is provided. The memory includes multiple word lines, and each of the plurality of word lines is coupled to a plurality of memory cells. The method includes: performing a first programming operation on a plurality of memory cells coupled to a selected word line among the multiple word lines, the first programming operation including applying a one-pulse to the selected word line to program the multiple memory cells coupled to the selected word line into N programmed states; and performing a second programming operation on the selected word line to program the multiple memory cells coupled to the selected word line into N target programmed states, where N is a positive integer.

Abstract: A memory includes a memory array and a peripheral circuit, wherein the memory array includes memory cells; the memory cells include a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line; and the peripheral circuit is configured to: acquire a grouping result of the plurality of second memory cells, and if a first memory cell is coupled with a second memory cell in a first group through a first bit line, apply a first read voltage to the first memory cell at a first read duration; and if a first memory cell is coupled with a second memory cell in a second group through a second bit line, apply a second read voltage to the first memory cell at a second read duration.

Abstract: A memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Abstract: The present disclosure provides a method of operating a memory, a memory, a memory system and an electronic device. In an example, a method of operating a memory is provided. The memory includes multiple word lines, and each of the plurality of word lines is coupled to a plurality of memory cells. The method includes: performing a first programming operation on a plurality of memory cells coupled to a selected word line among the multiple word lines, the first programming operation including applying a one-pulse to the selected word line to program the multiple memory cells coupled to the selected word line into N programmed states; and performing a second programming operation on the selected word line to program the multiple memory cells coupled to the selected word line into N target programmed states, where N is a positive integer.

Abstract: According to one aspect, a method of operating a memory is provided. The method may include applying a first power supply voltage to a common source during a program precharge process. The method may include applying a first voltage to a first bottom gate line and applying a second voltage to a second bottom gate line starting at a first moment of the program precharge process. The method may include applying a second power supply voltage to the first bottom gate line and applying a third voltage to the second bottom gate line after the first moment of the program precharge process.

Abstract: The present disclosure discloses a memory, a memory system, and a method for operating memory, which belongs to the memory techniques field. The method for operating memory comprises determining a storage state of a reference memory cell, determining a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell, and reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain read results. The target memory cell and the reference memory cell are located in the same string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell. The present disclosure may reduce the influence on reading memory cells by interlayer interference and improve the accuracy of reading memory cells.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for operating a memory device having multiple storage modes. In one example method, a portion of a memory array is selected, wherein the portion of the memory array is programmable in a first storage mode or a second storage mode. The second storage mode has a lower storage density than the first storage mode, and the first storage mode corresponds to a first erase operation. A switch erase operation is performed to switch the portion of the memory array from the first storage mode to a switched second storage mode, wherein the switched second storage mode has the same storage density as the second storage mode and corresponds to the switch erase operation. The switch erase operation is different from the first erase operation on the memory array in the first storage mode.

Abstract: In certain aspects, a memory device includes a memory string including a drain select gate (DSG) transistor, memory cells, and a source select gate (SSG) transistor, a bit line coupled to the DSG transistors, a source line coupled to the SSG transistor, and a peripheral circuit coupled to the memory string through the bit line and the source line. The peripheral circuit is configured to, in a pre-charge period of a program operation, apply a bias voltage to at least one of the bit line or the source line. The bias voltage is determined based on a temperature associated with the memory device.

Abstract: The present disclosure provides a memory device, a memory system, and an operation method of a memory device, and relates to the technical field of semiconductor chips. The memory device includes a memory cell array including a source layer, a bottom select gate layer, and a gate layer, and the bottom select gate layer is located between the source layer and the gate layer, wherein the bottom select gate layer includes a plurality of bottom select gates, and a bottom select gate of a first memory string and a bottom select gate of a second memory string are connected with a same select line; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to apply a selection voltage to the select line to control the first memory string and the second memory string.

Abstract: A data processing method, and a data processing model and a training method therefor are provided, and relate to the field of artificial intelligence, and specifically, to natural language processing, deep learning technologies, and large model technologies. An implementation solution includes: determining input data, where the input data includes a plurality of tokens; determining a correlation between each of the plurality of tokens and each of a plurality of expert networks based on a gating matrix, where the plurality of expert networks are used to reinforce the plurality of tokens; allocating the plurality of tokens to the plurality of expert networks in a uniform manner based on the correlation and a preset capacity of each expert network, to reinforce the plurality of tokens; and determining a data processing result based on the plurality of reinforced tokens.

Abstract: A method of operating a memory device includes applying a first program voltage to a selected word line corresponding to a target group of memory cells, applying a first verify voltage to the selected word line corresponding to the target group of memory cells, applying a pre-determined number of program pulses to the selected word line corresponding to a second memory cell of the target group of memory cells, and applying a first bit line bias voltage to a first bit line corresponding to the second memory cell of the target group of memory cells during applying a first or a last of the pre-determined number of program pulses to the selected word line corresponding to the second memory cell.

Abstract: Examples of the present disclosure provide a test device, a wafer, and a test method. The test device includes a control circuit connected to M groups of pads and N groups of test units, wherein M and N are both integers greater than 1; a number of test units included in each group of test units is less than or equal to M, and a total number of the test units is greater than M. The control circuit is configured to receive a test signal, select one of the N groups of test units based on the test signal, and connect at least some of the M groups of pads to the test units in the selected group of test units in one-to-one correspondence.

Abstract: A memory includes a memory array and a peripheral circuit, wherein the memory array includes memory cells; the memory cells include a plurality of first memory cells coupled with a first selected word line, and a plurality of second memory cells coupled with a second selected word line; and the peripheral circuit is configured to: acquire a grouping result of the plurality of second memory cells, and if a first memory cell is coupled with a second memory cell in a first group through a first bit line, apply a first read voltage to the first memory cell at a first read duration; and if a first memory cell is coupled with a second memory cell in a second group through a second bit line, apply a second read voltage to the first memory cell at a second read duration.

Abstract: An example memory device includes: memory cells constituting memory cell rows coupled to word lines and memory strings coupled to bit lines; and a peripheral circuit configured to: perform a read operation on the memory cells connected to a first word line to obtain at least two read values; during the read operation performed on the memory cells connected to the first word line, divide the memory cells connected to a second word line into at least two groups based on threshold voltages of the memory cells connected to the second word line; and determine read results of the memory cells connected to the first word line from the at least two read values based on grouping information of the memory cells connected to the second word line. The first word line and the second word line are word lines adjacent to each other.

Abstract: The present application discloses a memory, a memory system, and a method for operating memory, which belongs to the memory techniques field. The method for operating memory comprises determining a storage state of a reference memory cell, determining a discharge duration of a sensing node corresponding to a target memory cell based on the storage state of the reference memory cell, and reading the target memory cell based on the discharge duration of the sensing node corresponding to the target memory cell to obtain read results. The target memory cell and the reference memory cell are located in the same string and are adjacent, and the programming order of the reference memory cell is after that of the target memory cell. The present application may reduce the influence on reading memory cells by interlayer interference and improve the accuracy of reading memory cells.

Abstract: In certain aspects, a memory device includes memory cells and a peripheral circuit coupled to the memory cells. The memory cells include a first memory cell coupled to a first word line, a second memory cell coupled to a second word line, and a target memory cell coupled to a third word line adjacent to the first and second word lines. The peripheral circuit is configured to program the target memory cell, perform a first sample read on the first memory cell to obtain a first sample value of the first memory cell, configure one or more verification parameters of the target memory cell based on the first sample value, perform a second sample read on the second memory cell to obtain a second sample value of the second memory cell, and configure one or more read parameters of the target memory cell based on the second sample value.

Abstract: The present disclosure provides a memory device and an operation method thereof, a memory system, and a computer readable storage medium. The memory device includes: a memory array and a peripheral circuit coupled with the memory array. The memory array includes a plurality of memory cell strings and a conductive line coupled with one end of a memory cell string. The peripheral circuit is configured to: apply a first precharge voltage to the conductive line in a precharge stage of a first program cycle; and apply a second precharge voltage to the conductive line in a precharge stage of a second program cycle after the first program cycle, wherein the second precharge voltage is greater than the first precharge voltage.