Patents by Inventor Chenji ZOU

Chenji ZOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Qubit assembly, qubit assembly preparation method, chip, and device
    Patent number: 11917927
    Abstract: A production line device prepares a superconducting circuit layer on a substrate. The device prepares an under bump metallization (UBM) layer on an upper surface of the superconducting circuit layer. A superconducting connection is formed between the UBM layer and the superconducting circuit layer. The production device prepares a welding spot on an upper surface of the UBM layer to obtain a qubit assembly configured for a flip-chip superconducting quantum chip. A superconducting electrical connection is formed between the welding spot and the UBM layer.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: February 27, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Chenji Zou, Yarui Zheng, Hui Wang
  • QUBIT ASSEMBLY, QUBIT ASSEMBLY PREPARATION METHOD, CHIP, AND DEVICE
    Publication number: 20230115860
    Abstract: A production line device prepares a superconducting circuit layer on a substrate. The device prepares an under bump metallization (UBM) layer on an upper surface of the superconducting circuit layer. A superconducting connection is formed between the UBM layer and the superconducting circuit layer. The production device prepares a welding spot on an upper surface of the UBM layer to obtain a qubit assembly configured for a flip-chip superconducting quantum chip. A superconducting electrical connection is formed between the welding spot and the UBM layer.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 13, 2023
    Inventors: Chenji ZOU, Yarui ZHENG, Hui WANG
  • Transistor devices and methods of forming a transistor device
    Patent number: 11282953
    Abstract: According to various embodiments, a transistor device may include a substrate. The transistor device may further include a drain terminal and a source terminal formed in the substrate, and a gate terminal formed over the substrate. The transistor device may further include an insulator structure arranged between the drain terminal and the source terminal, and at least partially under the gate terminal. The insulator structure may include an oxide member and a trench isolation region. The oxide member may be at least partially formed over the trench isolation region.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 22, 2022
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Ming Li, Sivaramasubramaniam Ramasubramaniam, Dong Hyun Shin, Di Wu, Yunpeng Xu, Chenji Zou, Jeoung Mo Koo
  • TRANSISTOR DEVICES AND METHODS OF FORMING A TRANSISTOR DEVICE
    Publication number: 20210320203
    Abstract: According to various embodiments, a transistor device may include a substrate. The transistor device may further include a drain terminal and a source terminal formed in the substrate, and a gate terminal formed over the substrate. The transistor device may further include an insulator structure arranged between the drain terminal and the source terminal, and at least partially under the gate terminal. The insulator structure may include an oxide member and a trench isolation region. The oxide member may be at least partially formed over the trench isolation region.
    Type: Application
    Filed: April 14, 2020
    Publication date: October 14, 2021
    Inventors: Ming LI, Sivaramasubramaniam RAMASUBRAMANIAM, Dong Hyun SHIN, Di WU, Yunpeng XU, Chenji ZOU, Jeoung Mo KOO