Patents by Inventor CHENLONG MIAO

CHENLONG MIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11728192
    Abstract: An optical inspection is performed to detect potential defects within integrated circuit devices and a first electron-based inspection of less than all of the potential defects is performed to identify primary actual defects. A process window of manufacturing parameter settings used to manufacture the integrated circuit devices is identified and the integrated circuit devices manufactured using the manufacturing parameter settings inside the process window have less than a threshold number of the primary actual defects. To identify additional actual defects a second electron-based inspection is performed that is limited to selected ones of the potential defects in the integrated circuit devices that were manufactured using the manufacturing parameter settings inside the process window but were uninspected in the first electron-based inspection.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: August 15, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Chenlong Miao, Haizhou Yin, Michael J. Wojtowecz
  • Publication number: 20230024266
    Abstract: An optical inspection is performed to detect potential defects within integrated circuit devices and a first electron-based inspection of less than all of the potential defects is performed to identify primary actual defects. A process window of manufacturing parameter settings used to manufacture the integrated circuit devices is identified and the integrated circuit devices manufactured using the manufacturing parameter settings inside the process window have less than a threshold number of the primary actual defects. To identify additional actual defects a second electron-based inspection is performed that is limited to selected ones of the potential defects in the integrated circuit devices that were manufactured using the manufacturing parameter settings inside the process window but were uninspected in the first electron-based inspection.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 26, 2023
    Applicant: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Chenlong Miao, Haizhou Yin, Michael J. Wojtowecz
  • Publication number: 20220196580
    Abstract: The embodiments herein relate to defect inspection methods of semiconductor wafers during the manufacturing process. According to an aspect of the present disclosure, a defect inspection system is provided. The defect inspection system includes a first inspection system, pattern simulator software, and a second inspection system. The first inspection system is capable of determining a plurality of defect locations on an article. The pattern simulator software is capable of generating a set of simulated pattern features from the plurality of defect locations. The second inspection system is capable of providing a higher graphical resolution of defects than the first inspection at the defect locations corresponding to the set of simulated pattern features.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: HAIZHOU YIN, CHENLONG MIAO, SHAO WEN GAO, MICHAEL WOJTOWECZ, TAMER DESOUKY