Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns.

Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Abstract: Tracking patterns during a semiconductor fabrication process includes: obtaining an image of a portion of a fabricated device; extracting contours of the portion of the fabricated device from the obtained image; aligning the extracted contour to a matching section of a reference design; decomposing the matching section of the reference design into one or more patterns; and updating a pattern tracking database with information pertaining to at least one pattern in the one or more patterns generated as a result of the decomposition.

Abstract: An integrated-circuit yield improvement system includes a global signature analysis/grouping module configured to receive an integrated circuit (IC) design and identify areas in the IC design that include potential defect signatures based on the defect signatures stored in the defect signature library. The global signature analysis/grouping module can produce a global signature map indicating these areas and their associated potential defect signatures in the IC design. A local signature analysis/grouping module can identify and group local defect signatures in the IC design with the process monitoring and yield data as input, to output grouped local signatures. An intelligent learning engine can analyze the global signature map and the grouped local signatures and update some of the defect signatures in the defect signature library. A feedback loop is formed to update and renew the contents of the defect signature library for each new IC design while process and yield are improved.