Patents by Inventor Chenmin Zhang
Chenmin Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9424127Abstract: Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.Type: GrantFiled: July 25, 2013Date of Patent: August 23, 2016Assignee: BROADCOM CORPORATIONInventors: Walid Nabhane, Mark D Rutherford, Narayan Prasad Ramachandran, David Chang, Yi Ting Chen, Chenmin Zhang, Ajmal A. Godil
-
Patent number: 8989331Abstract: Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.Type: GrantFiled: May 31, 2007Date of Patent: March 24, 2015Assignee: Broadcom CorporationInventors: Sam H. Liu, Zhiqing Zhuang, Chaoyang Zhao, Vinay Bhasin, Chenmin Zhang, Lawrence J. Madar, III, Vafa J. Rakshani
-
Patent number: 8909956Abstract: A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.Type: GrantFiled: June 10, 2010Date of Patent: December 9, 2014Assignee: Broadcom CorporationInventors: Zhiqing Zhuang, Vinay Kumar Bhasin, Lawrence John Madar, III, Chenmin Zhang, Vafa James Rakshani, Soheyla Kamal
-
Publication number: 20140223200Abstract: Aspects of charger detection and optimization prior to host control are described herein. In various embodiments, a condition of whether reverse current is present on a system bus is detected. When the condition for reverse current is present, reverse current is sunk by one or more of various reverse current sink circuits. By relying upon one or more of the reverse current sink circuits, for safety, to address or mitigate the condition for reverse current, a detector may be able to identify or distinguish among several different types of charger or charging ports coupled to a system bus allowing a charger to be selected optimally. Further, an indicator of the type of charger or charging port coupled to the system bus is communicated over a single pin interface, for backwards compatibility with circuits capable of identifying between only two different types of chargers.Type: ApplicationFiled: July 25, 2013Publication date: August 7, 2014Inventors: Walid Nabhane, Mark D. Rutherford, Narayan Prasad Ramachandran, David Chang, Yi Ting Chen, Chenmin Zhang, Ajmal A. Godil
-
Publication number: 20100257393Abstract: A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.Type: ApplicationFiled: June 10, 2010Publication date: October 7, 2010Applicant: Broadcom CorporationInventors: Zhiqing Zhuang, Jalil Fadavi-Ardekani, Soheyla Kamal, Vinay Kumar Bhasin, Lawrence John Madar, III, Chenmin Zhang, Vafa James Rakshani
-
Patent number: 7739528Abstract: A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.Type: GrantFiled: July 31, 2006Date of Patent: June 15, 2010Assignee: Broadcom CorporationInventors: Zhiqing Zhuang, Jalil Fadavi-Ardekani, Soheyla Kamal, legal representative, Vinay Kumar Bhasin, Lawrence John Madar, III, Chenmin Zhang, Vafa James Rakshani
-
Publication number: 20100070659Abstract: Aspects of a method and system for operating and/or charging a battery powered USB device based on a USB port type are provided. In this regard, in a USB device comprising a power management IC and a multi-function IC, a port type detection module in the multi-function IC may determine whether the USB device is attached to a standard host port or a charging port. Additionally, a power source in the power management IC, which may supply power to the port type detection module, may be enabled upon attachment of the USB device to a USB port and disabled subsequent to determination of port type. Also, one or more portions and/or functions of the power management IC may be configured based on the determined port type. Similarly, one or more portions and/or functions of the multi-function IC may be enabled or disabled based on the determined port type.Type: ApplicationFiled: November 5, 2008Publication date: March 18, 2010Inventors: Kenneth Ma, Chenmin Zhang, Alfonsus Lunardhi, Manisha Pandya, Shimon Elkayam
-
Patent number: 7391788Abstract: Aspects of the invention provide a method and system for a communication bus for resetting one or more devices connected to the bus. The transceiver bus (620) may include a single serial data line (616), a single serial clock line (614) and a single reset line (612). A status of a slave device coupled to the transceiver bus (620) may be determined by a master device. Based on the status of the slave device, the master device may execute a forced reset or a normal reset. In a case where a device may be unresponsive, the master device may execute a forced reset. Additionally, in a case where a device is responsive but requires resetting, the master device may execute a normal reset and selectively reset a slave device requiring reset.Type: GrantFiled: November 19, 2002Date of Patent: June 24, 2008Assignee: Broadcom CorporationInventors: Chenmin Zhang, Steve Thomas, Randall Stolaruk
-
Publication number: 20070288778Abstract: A state machine and an external interface, including its associated input-outputs (IOs), are always powered on and used to manage the chip power modes and power mode transitions. The chip power modes are defined as RUN, HIBERNATE, POWERDOWN, with many more possible with this invention. For example, once the device is in HIBERNATE or POWERDOWN modes, the power supplies to the IC are either reduced, or completely disconnected except for this controller state machine. This invention's state machine and control mechanism, in response to some external “wake up event”, will bring the chip to RUN mode by managing the state of the external power supplies through its control interface. The implementation achieves small die size and extreme low power consumption.Type: ApplicationFiled: July 31, 2006Publication date: December 13, 2007Applicant: Broadcom CorporationInventors: Zhiqing Zhuang, Jalil Fadavi-Ardekani, Soheyla Kamal, Vinay Kumar Bhasin, Lawrence John Madar, Chenmin Zhang, Vafa James Rakshani
-
Publication number: 20070280396Abstract: Provided is a method for transferring data from one clock domain within a synchronizer to another domain within the synchronizer. The method includes determining system clock parameters within the synchronizer and analyzing a first domain clock signal based upon the system clock parameters. Next, a second domain clock signal is analyzed based upon the first domain clock signal and the system clock parameters. A determination is made as to when to transfer data from a first clock domain to a second clock domain in accordance with the analysis of the first and second domain clock signals, and an enable signal is provided to affect the data transfer from the first domain to the second clock domain.Type: ApplicationFiled: May 31, 2007Publication date: December 6, 2007Applicant: Broadcom CorporationInventors: Sam H. Liu, Zhiqing Zhuang, Chaoyang Zhao, Vinay Bhasin, Chenmin Zhang, Lawrence J. Madar, Vafa J. Rakshani
-
Publication number: 20040095952Abstract: Aspects of the invention provide a method and system for a communication bus for resetting one or more devices connected to the bus. The transceiver bus (620) may include a single serial data line (616), a single serial clock line (614) and a single reset line (612). A status of a slave device coupled to the transceiver bus (620) may be determined by a master device. Based on the status of the slave device, the master device may execute a forced reset or a normal reset. In a case where a device may be unresponsive, the master device may execute a forced reset. Additionally, in a case where a device is responsive but requires resetting, the master device may execute a normal reset and selectively reset a slave device requiring reset.Type: ApplicationFiled: November 19, 2002Publication date: May 20, 2004Inventors: Chenmin Zhang, Steve Thomas, Randall Stolaruk
-
Patent number: 6226777Abstract: An improved integrated circuit design tool allows the incorporation of minor revisions to a high level register transfer language (RTL) code (netlist) by incorporating within a formal verification tool an engineering change order (ECO) compiler. The addition of the ECO compiler to the formal verification tool eliminates the need to rerun a synthesis tool after minor changes to a revised RTL netlist in order to generate a revised gate (logic) level netlist.Type: GrantFiled: November 25, 1998Date of Patent: May 1, 2001Assignee: Agilent Technologies, Inc.Inventor: Chenmin Zhang
-
Patent number: 6163867Abstract: A method and a system for testing integrated devices such as chips used on a printed circuit board. The system includes test logic formed on the chip and coupled to bi-directional input/output pads. The system is capable of testing input pads, output pads, and bi-directional pads by coupling an input test signal from one pad of a pair of pads to the output of a second pad of the pair of pads. If the signal read out of the second pad corresponds to the expected value, the pads may be considered properly connected. The chips may be tested at any stage during chip manufacture, including after forming the die on a wafer, after cutting the die from the wafer and after packaging the die to produce the chip, and after attaching the chip to a printed circuit board. The system and method allow for quick and easy testing of pad connectivity during the manufacturing process, while minimizing the number of extra gates and trace lines on the chip.Type: GrantFiled: August 28, 1998Date of Patent: December 19, 2000Assignee: Hewlett-Packard CompanyInventors: John Miller, Richard Ortiz, Chenmin Zhang