Abstract: A technique for reducing the overhead of daisy chain test mode in divide-and-conquer testing using intermediate test modes that do not span all cores or all flip-flops in the core. The partial residual test mode spans across a subset of the cores and allows to bound the number of cores that a full residual test mode may span across. The interaction of the cores among one another at the top-level is analyzed and the minimum number of flip-flops in a core that must participate in a intermediate test mode is selected. Algorithms are devised to analyze the interactions among the cores and build data structures which are used for identifying intermediate test modes. Using a reconfigurable scan segment architecture, intermediate test modes are implemented that are designed to work with all known test compression solutions.

Abstract: A method and/or a system of at-speed transition fault testing with low speed scan enable is disclosed. In one embodiment, a digital system includes any number of scan chains. Each scan chain may have any number of scan cells, an at-speed local scan enable signal to control a mode of operation, and any number of last transition generator cells. In addition, each last transition generator cell includes a first flip-flop with an output connected to a second flip-flop input, an input multiplexer to apply any one of a first flip-flop output data and an OR gate having a first flip-flop input based on a state of the at-speed local scan enable signal, and an OR gate having a first flip-flop output and the global scan enable signal as inputs to generate the at-speed local scan enable signal based on a state of the global scan enable signal.