Patents by Inventor Chenrong Xiong

Chenrong Xiong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967971
    Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.
    Type: Grant
    Filed: March 2, 2023
    Date of Patent: April 23, 2024
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Chenrong Xiong, Jie Chen
  • Patent number: 11923028
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Grant
    Filed: November 3, 2022
    Date of Patent: March 5, 2024
    Inventors: Chenrong Xiong, Jie Chen
  • Publication number: 20240014830
    Abstract: Systems and methods are provided for estimating LLR values used for soft decoding of data stored in non-volatile storage devices. A method may include reading data stored in a non-volatile storage device using a group of soft read reference voltages, decoding the data read from the non-volatile storage device in a soft decoding process, obtaining a number of ones and a number of zeros for each zone of a plurality of zones delineated by the group of soft read reference voltages and obtaining a log-likelihood ratios (LLR) for each zone of the plurality of zones based on a ratio of the number of ones to the number of zeros in each zone.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Chenrong XIONG, Jie CHEN
  • Publication number: 20240013849
    Abstract: Systems and methods are provided for determining optimal read reference voltages used for reading data in non-volatile storage devices. A method may include reading data stored in a non-volatile storage device using a group of soft read reference voltages, decoding the data and obtaining the number of ones and number of zeros for each of a plurality of zones delineated by the soft read reference voltages, determining that one of the soft read reference voltages is a boundary of a zone in which a comparison result of the number of ones compared to the number of zeros is greater than zero and a boundary of another zone in which a comparison result is less than zero and setting the soft read reference voltage adjusted by an adjustment as an optimal read reference voltage. The adjustment may be obtained based on the two comparison results.
    Type: Application
    Filed: July 6, 2022
    Publication date: January 11, 2024
    Inventors: Chenrong XIONG, Jie CHEN
  • Publication number: 20230231579
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 20, 2023
    Inventors: Kyoung Lae CHO, Soo Jin KIM, Naveen KUMAR, Aman BHATIA, Yi-Min LIN, Chenrong XIONG, Fan ZHANG, Yu CAI, Abhiram PRABAHKAR
  • Publication number: 20230208447
    Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.
    Type: Application
    Filed: March 2, 2023
    Publication date: June 29, 2023
    Inventors: Chenrong XIONG, Jie CHEN
  • Patent number: 11621728
    Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 4, 2023
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Chenrong Xiong, Jie Chen
  • Publication number: 20230086057
    Abstract: Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include an aggregation mode for aggregating read results of multiple reads. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.
    Type: Application
    Filed: November 12, 2022
    Publication date: March 23, 2023
    Inventors: Han ZHANG, Chenrong XIONG, Jie CHEN
  • Patent number: 11610116
    Abstract: Disclosed is a computer-implemented method for optimizing read thresholds of a memory device using a deep neural network engine, comprising reading, using a set of read threshold voltages applied to the memory device, data from the memory device under a first set of operating conditions that contribute to read errors in the memory device, producing a labeled training data set using the set of read threshold voltages under the first set of the operating conditions, determining, based on characteristics of the memory device, a number of layers, a size of each layer, and a number of input and output nodes of the deep neural network engine, training the deep neural network engine using the labeled training data set, and using the trained deep neural network engine to compute read thresholds voltage values under a second set of operating conditions.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Yu Cai, Chenrong Xiong, Xuanxuan Lu
  • Patent number: 11611359
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: March 21, 2023
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Publication number: 20230078705
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Application
    Filed: November 3, 2022
    Publication date: March 16, 2023
    Inventors: Chenrong XIONG, Jie CHEN
  • Patent number: 11528039
    Abstract: Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating read results of multiple reads, and whether the read results include soft data. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: December 13, 2022
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Han Zhang, Chenrong Xiong, Jie Chen
  • Patent number: 11521700
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 6, 2022
    Assignee: INNOGRIT TECHNOLOGIES co., LTD.
    Inventors: Chenrong Xiong, Jie Chen
  • Publication number: 20220385309
    Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: Chenrong XIONG, Jie CHEN
  • Patent number: 11515897
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Publication number: 20220302932
    Abstract: Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating read results of multiple reads, and whether the read results include soft data. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 22, 2022
    Inventors: Han ZHANG, Chenrong XIONG, Jie CHEN
  • Patent number: 11444637
    Abstract: Disclosed are methods, systems and devices for decoding data read from a memory device, including receiving noisy data from a first memory location included in a word line zone of the memory device, identifying the word line zone and a prior successful decoder parameter associated with the word line zone, decoding the noisy data using the prior successful decoder parameter used in a prior successful decoding with respect to a second memory location included in the same word line zone, determining whether the decoding based on the prior successful decoder parameter has succeeded, maintaining, upon a determination that the decoding has succeeded, the prior successful decoder parameter as a decoder parameter for the first memory location, and decoding, upon a determination that the decoding operation has failed, the noisy data read from the first memory location by using another decoder parameter selected from a set of predefined decoder parameters.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Xuanxuan Lu
  • Publication number: 20220215894
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Chenrong XIONG, Jie CHEN
  • Patent number: 11367488
    Abstract: A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Chenrong Xiong, Fan Zhang, Naveen Kumar, Xuanxuan Lu, Yu Cai
  • Patent number: 11356123
    Abstract: Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi