Patents by Inventor Chenrong Xiong

Chenrong Xiong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11528039
    Abstract: Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating read results of multiple reads, and whether the read results include soft data. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: December 13, 2022
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Han Zhang, Chenrong Xiong, Jie Chen
  • Patent number: 11521700
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 6, 2022
    Assignee: INNOGRIT TECHNOLOGIES co., LTD.
    Inventors: Chenrong Xiong, Jie Chen
  • Publication number: 20220385309
    Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.
    Type: Application
    Filed: June 1, 2021
    Publication date: December 1, 2022
    Inventors: Chenrong XIONG, Jie CHEN
  • Patent number: 11515897
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Soo Jin Kim, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Publication number: 20220302932
    Abstract: Systems and methods are provided for performing error recovery using LLRs generated from multi-read operations. A method may comprise selecting a set of decoding factors for a multi-read operation to read a non-volatile storage device multiple times. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating read results of multiple reads, and whether the read results include soft data. The method may further comprise issuing a command to the non-volatile storage device to read user data according to the set of decoding factors, generating a plurality of Log-Likelihood Ratio (LLR) values using a mapping engine from a pre-selected set of LLR value magnitudes based on the set of decoding factors, obtaining an aggregated read result in accordance with the aggregation mode and obtaining an LLR value from the plurality of LLR values using the aggregated read result as an index.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 22, 2022
    Inventors: Han ZHANG, Chenrong XIONG, Jie CHEN
  • Patent number: 11444637
    Abstract: Disclosed are methods, systems and devices for decoding data read from a memory device, including receiving noisy data from a first memory location included in a word line zone of the memory device, identifying the word line zone and a prior successful decoder parameter associated with the word line zone, decoding the noisy data using the prior successful decoder parameter used in a prior successful decoding with respect to a second memory location included in the same word line zone, determining whether the decoding based on the prior successful decoder parameter has succeeded, maintaining, upon a determination that the decoding has succeeded, the prior successful decoder parameter as a decoder parameter for the first memory location, and decoding, upon a determination that the decoding operation has failed, the noisy data read from the first memory location by using another decoder parameter selected from a set of predefined decoder parameters.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Xuanxuan Lu
  • Publication number: 20220215894
    Abstract: Systems and methods are provided for tracking read reference voltages used for reading data in a non-volatile storage device. A method may comprise collecting pre-decoding state information for a read reference voltage by reading data stored in a non-volatile storage device using the read reference voltage, collecting post-decoding state information for the read reference voltage after decoding the data, generating a comparison of probability of state errors for the read reference voltage based on the pre-decoding state information and post-decoding state information, obtaining an adjustment amount to the read reference voltage based on the comparison of probability of state errors; and adjusting the read reference voltage by applying the adjustment amount to the read reference voltage to obtain an adjusted read reference voltage.
    Type: Application
    Filed: January 4, 2021
    Publication date: July 7, 2022
    Inventors: Chenrong XIONG, Jie CHEN
  • Patent number: 11367488
    Abstract: A memory system includes a memory device and a controller. The controller determines a target word line group to which a target word line corresponding to a read command belongs. The controller identifies a reference voltage corresponding to the target word line group. The controller controls the memory device to perform a read operation on a target page coupled to the target word line, using the reference voltage.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: June 21, 2022
    Assignee: SK hynix Inc.
    Inventors: Aman Bhatia, Chenrong Xiong, Fan Zhang, Naveen Kumar, Xuanxuan Lu, Yu Cai
  • Patent number: 11356123
    Abstract: Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: June 7, 2022
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11321175
    Abstract: Techniques are described for memory writes and reads according to a chip-kill scheme that allows recovery of multiple failed wordlines. In an example, when reading data from a superblock of the memory, where the decoding of multiple wordlines failed, a computer system schedules the decoding of failed wordlines based on quantity of bit errors and updates soft information based on convergence or divergence of the scheduled decoding. Such a computer system significantly reduces decoding failures associated with data reads from the memory and allows improved data retention in the memory.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Naveen Kumar, Aman Bhatia, Chenrong Xiong, Yu Cai, Fan Zhang
  • Patent number: 11271589
    Abstract: Memory controllers bit-flipping (BF) decoders and methods that selectively apply a checksum-aided error reduction (CA-ER) scheme to BF decoding of a low-density parity-check (LDPC) code. In decoding a codeword, a hard decision value resulting from decoding a select variable node is changed when a first condition is satisfied to yield an updated hard decision value. Also, when the first condition is satisfied, a current checksum value after processing the select variable node is updated using the updated hard decision value. The CA-ER scheme is applied when the updated checksum value is not reduced to a set minimum and a second condition based on a previous checksum value, calculated after a previous variable node is processed, is satisfied.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: March 8, 2022
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11210008
    Abstract: A memory system includes a memory device and a controller. The controller performs multiple read operations on a target block, using a first duster of read threshold voltages. The controller generates a second duster of read threshold voltages using the first cluster when a difference between the maximum number of fail bits and the minimum number of fail bits associated with the multiple read operations exceeds a threshold. The controller splits pages in the target block into a first group of pages for the first cluster and a second group of pages for the second cluster. The controller performs additional read operations on the first group of pages using the first cluster and on the second group of pages using the second cluster.
    Type: Grant
    Filed: January 20, 2020
    Date of Patent: December 28, 2021
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Xuanxuan Lu
  • Patent number: 11204839
    Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: December 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11184024
    Abstract: Disclosed are devices, systems and methods for improving a bit-flipping algorithm for an irregular LDPC code in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated from an irregular low-density parity-check code, performing a first iteration of a bit-flipping algorithm on the noisy codeword, computing a first syndrome based on an output codeword of the first iteration, determining that the first syndrome comprises a non-zero vector and no bits of the noisy codeword were flipped during the first iteration of the bit-flipping algorithm, flipping, based on the determining, at least one bit of the output codeword, the at least one bit corresponding to a variable node of the plurality of variable nodes with a smallest column weight connected to one or more unsatisfied check nodes of the plurality of check nodes, and computing, subsequent to the flipping, a second syndrome.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Fan Zhang, Haobo Wang, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11177835
    Abstract: A data processing system includes a storage medium, and a controller including a data processing block, configured to receive data from a host, transmit the received data to the storage medium, read data from the storage medium in response to a read request from the host, and decode the read data by the data processing block according to multiple decoding modes. The data processing block includes a first decoder and a second decoder, and is configured to manage the first decoder and the second decoder to run the decoding for the read data, and activate a fast decoding having shorter latency than a normal decoding after a fast decoding condition is satisfied.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyoung Lae Cho, Naveen Kumar, Aman Bhatia, Yi-Min Lin, Chenrong Xiong, Fan Zhang, Yu Cai, Abhiram Prabahkar
  • Patent number: 11146290
    Abstract: The present disclosure provides an improved bit-flipping method and system for decoding a received LDPC codeword. The decoding process may include estimating values with respect to the bits of the received LDPC codeword by a plurality of bit nodes and check nodes. A flipping energy of a bit node may be obtained based on a function of values of check nodes connected to it. Then, a flipping reliability of the bit node may be determined by comparing the flipping energy with at least one flipping energy threshold. Further, a flipping probability of the bit node may be determined based on the flipping reliability and a flipping rule. A flipping test may be performed according to the flipping probability, and as a result, at least one target bit node that is required to be flipped may be determined and further flipped.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 12, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Chenrong Xiong, Jie Chen, Zining Wu
  • Patent number: 11139831
    Abstract: Disclosed are devices, systems and methods for improving fast fail support for error correction in non-volatile memory. An exemplary method includes (a) receiving a codeword from a read operation in a fast fail mode, (b) initially configuring a maximum number of iterations (Nmax) and a set of values for a plurality of bit flipping thresholds for performing a decoding operation on the codeword, (c) performing a plurality of decoding iterations (N), each iteration using a subset of bit flipping thresholds, (d) calculating a remaining number of iterations (Nrem) as a difference between Nmax and N, (e) reconfiguring, based on Nrem and a latency requirement of the read operation in the fast fail mode, the set of values for the plurality of bit flipping thresholds to restart the decoding operation, and (f) repeating operations (c) through (e) until the codeword is successfully decoded or Nrem is less than or equal to 0.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Xuanxuan Lu, Meysam Asadi
  • Patent number: 11127471
    Abstract: Embodiments describe a method for reading data from storage that includes selecting a block of memory to read, identifying a read retry table for reading the block, determining that the read retry table for the selected block of memory needs to be updated, and reading the block of memory using a new set of read threshold voltages from the read retry table. Responsive to a successful read operation using the new set of voltages, the method can also include replacing the initial set of read voltages in the first field with the new set of read voltages, and filling the plurality of subsequent fields in the read retry table with additional sets of read threshold voltages identified from a read retry neighbor table, where at least one of the additional sets of read voltages is closest in distance to the initial set of read voltages in read voltage space.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Xuanxuan Lu, Fan Zhang, Chenrong Xiong, Haobo Wang, Meysam Asadi
  • Patent number: 11128314
    Abstract: Techniques related to improving a performance related to at least data reads from a memory are described. In an example, data is stored in a block of the memory as codewords. A data read includes a determination of whether each bit from a portion of the block is a zero or a one based on voltage measurements. Prior to decoding the codewords by performing a decoding procedure by an ECC decoder of the memory, a first number of errors “E01” and a second number of errors “E10” are estimated, where the first number of errors “E01” is associated with bits each being a true zero and erroneously determined as a one, and where the second number of errors “E10” associated with bits each being a true one and erroneously determined as a zero. Thereafter, the decoding of the codewords based on the decoding procedure is performed.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 21, 2021
    Assignee: SK hynix Inc.
    Inventors: Fan Zhang, Chenrong Xiong, Meysam Asadi, Xuanxuan Lu
  • Publication number: 20210263799
    Abstract: Multiple memory systems with respective decoders employ a low latency implementation of a read recovery level feature in decoding data. The decoding comprises receiving from a host a read request for decoding read data at a first recovery level by a first memory system, a first decoder of the first memory system being set at a second recovery level with a corresponding maximum iteration number when the read request is received by the first memory system; and operating the first decoder, after a set time elapses, to decode the read data at the second recovery level. A second decoder of a second memory system is set at the first recovery level for at least part of the time during which the first decoder operates to decode the read data at the second recovery level.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 26, 2021
    Inventors: Chenrong XIONG, Fan ZHANG, Haobo WANG, Xuanxuan LU, Meysam ASADI