Abstract: Disclosed are techniques for determining a threshold number of read operations on memory depending on one or more conditions of the memory. If a number of read operations for the memory meets the threshold number of read operations, a read reclaim operation can be performed to preserve data stored therein.

Abstract: Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.

Abstract: An apparatus of a semiconductor memory system and an operating method thereof include: a plurality of memory devices; and a controller coupled with the memory devices, the controller including a training data storage, a classifier trainer, and a decoder, is configured to perform decoding iterations, wherein the training data storage configured to collect and store at least training data, the classifier trainer configured to train classifiers at least with the training data, and the decoder configured to decode code-bits in accordance with rules of the classifier.

Abstract: A memory device for generating a mapping between one or more unusable columns and one or more backup columns within a memory. The memory includes a plurality of memory cells for storing data. The memory also includes a plurality of columns including a first subset of the plurality of memory cells. Each of the plurality of columns belongs to one of a plurality of data chunks. The memory further includes one or more backup columns including a second subset of the plurality of memory cells. The memory device also includes a controller communicatively coupled to the memory and configured to perform operations including identifying unusable columns, detecting a condition associated with each data chunk, and generating a mapping between the backup columns and the unusable columns based on the condition such that each of the backup columns is mapped to a different unusable column.

Abstract: Disclosed are techniques for selecting one or more reference voltages for performing one or more operations on a memory cell based on a determined layer of a three-dimensional memory construct to which the memory cell belongs. The one or more operations can include read or write operations. The memory cell can be a flash memory cell.

Abstract: A memory device for generating a mapping between one or more unusable columns and one or more backup columns within a memory. The memory includes a plurality of memory cells for storing data. The memory also includes a plurality of columns including a first subset of the plurality of memory cells. Each of the plurality of columns belongs to one of a plurality of data chunks. The memory further includes one or more backup columns including a second subset of the plurality of memory cells. The memory device also includes a controller communicatively coupled to the memory and configured to perform operations including identifying unusable columns, detecting a condition associated with each data chunk, and generating a mapping between the backup columns and the unusable columns based on the condition such that each of the backup columns is mapped to a different unusable column.

Abstract: An apparatus of a memory system and an operating method thereof includes a plurality of memory devices; and a controller coupled with the plurality of memory devices, configured to determine a range of read reference voltages having a plurality of read reference voltages, the read reference voltages achieving a minimal rBER; calculate an optimal read reference voltage in accordance with at least the range of read reference voltages; achieve a rBER in accordance with at least the optimal read reference voltage; and execute error correction process with at least the optimal read reference voltage.

Abstract: Disclosed are techniques for determining a threshold number of read operations on memory depending on one or more conditions of the memory. If a number of read operations for the memory meets the threshold number of read operations, a read reclaim operation can be performed to preserve data stored therein.

Abstract: Techniques for codeword decoding are described. In an example, a system accesses information about a block of a storage device of the system. The block includes data lines and redundant lines. The data lines are available to store data and include a bad data line that is unreliable for data storage. The redundant lines include a redundant line that replaces the bad data line, and a free redundant line that remains available after replacement of all bad data lines from the data lines. The information includes an identifier of the bad data line and an identifier of the free redundant line. The system accesses a codeword stored in the block. A portion of the codeword is stored in the free redundant line. The system decodes the codeword based on the identifier of the bad data line and the identifier of the free redundant line.

Abstract: A memory device including a memory having a plurality of memory cells for storing data. The memory device includes a controller communicatively coupled to the memory and configured to organize the data as a plurality of stripes. Each individual stripe of the plurality of stripes includes a plurality of data groups, each of the plurality of data groups stored in the memory using a subset of the plurality of memory cells. Stripe lengths (number of data groups) for individual stripes are determined by the controller based on detecting a condition associated with one or more data groups of the plurality of data groups. At least one data group of the plurality of data groups for each of the individual stripes includes parity data for correcting bit errors associated with the subset of the plurality of memory cells for the individual stripe.