Patents by Inventor Chenson Chen

Chenson Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418350
    Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 17, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Patent number: 10079224
    Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corresponding method for fabricating a semiconductor structure is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 18, 2018
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Patent number: 9780075
    Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: October 3, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Publication number: 20170200700
    Abstract: A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Application
    Filed: August 11, 2015
    Publication date: July 13, 2017
    Applicant: Massachusetts Institute of Technology
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Publication number: 20170162550
    Abstract: A semiconductor structure includes at least two substrate layers, each of the at least two substrate layers having first and second opposing surfaces and a plurality of electrical connections extending between the first and second surfaces. The semiconductor structure also includes a substrate joining layer disposed between and coupled to the second surface of a first one of the at least two substrate layers and the first surface of a second one of the at least two substrate layers. The substrate joining layer includes at least one integrated circuit (IC) structure disposed between the first and second surfaces of said substrate joining layer. A corres ponding method for fabricating a semiconductor structure is also provided.
    Type: Application
    Filed: August 11, 2015
    Publication date: June 8, 2017
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast
  • Publication number: 20170162507
    Abstract: A multi-layer semiconductor device includes at least a first semiconductor structure and a second semiconductor structure, each having first and second opposing surfaces. The second semiconductor structure includes a first section and a second section, the second section including a device layer and an insulating layer. The second semiconductor structure also includes one or more conductive structures and one or more interconnect pads. Select ones of the interconnect pads are electrically coupled to select ones of the conductive structures. The multi-layer semiconductor device additionally includes one or more interconnect structures disposed between and coupled to select portions of second surfaces of each of the first and second semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
    Type: Application
    Filed: August 11, 2015
    Publication date: June 8, 2017
    Inventors: Rabindra N. Das, Donna-Ruth W. Yost, Chenson Chen, Keith Warner, Steven A. Vitale, Mark A. Gouker, Craig L. Keast