Abstract: Disclosed in the present invention are a low-temperature coefficient ring oscillator, a chip, and a communication terminal. The low-temperature coefficient ring oscillator comprises a temperature tracking compensation circuit, an inverter oscillation circuit, and a buffer shaping circuit. The temperature characteristics of the impedance of a PMOS tube and an NMOS tube in an inverter in the inverter oscillation circuit are tracked and compensated for by means of the impedance, along with temperature change, of a PMOS tube and a NMOS tube connected by a diode.

Abstract: Disclosed in the present invention are a charge pump circuit, a chip, and a communication terminal. The charge pump circuit comprises a phase clock generation module, an acceleration response control module, and a plurality of sub charge pump modules. By generating a plurality of clock signals with a fixed phase difference by means of the phase clock generation module, correspondingly controlling the plurality of sub charge pump modules to generate output voltages, and by means of the acceleration response control module, measuring the output voltage of each sub charge pump module, and separately outputting a logic signal to the phase clock generation module and each sub charge pump module, the frequency of the clock signals outputted by the phase clock generation module is changed, and the charge and discharge time of a capacitor in each sub charge pump module is reduced.

Abstract: Disclosed are an on-chip RC oscillator, a chip, and a communication terminal. The on-chip RC oscillator comprises a stabilized voltage supply module, an RC core oscillator module, a frequency sampling and conversion module, and a frequency trimming module. By means of the frequency sampling and conversion module, the clock frequency of the oscillator is sampled and detected in real time, and the sampled clock frequency is converted into a voltage signal, and then analog-to-digital conversion is performed to obtain a corresponding digital code, so that when the clock frequency changes, the frequency trimming module circuit converts said digital code into a control signal; a voltage having a suitable temperature coefficient is outputted for the RC core oscillator module; also, a zero temperature coefficient current of a suitable magnitude is outputted for the RC core oscillator module, so as to precisely calibrate the clock frequency.

Abstract: An LD0 circuit having a power supply rejection function, a chip, and a communication terminal. The LD0 circuit comprises a bandgap reference module (101) provided with an intermediate frequency zero adjustment unit (109), an amplification module (102) provided with an intermediate frequency zero generation unit (105), and a power output module (103). The bandgap reference module (101) is connected to the amplification module (102), and the amplification module (102) is connected to the power output module (103). For the purpose of power supply rejection at an intermediate frequency, the intermediate frequency zero adjustment unit (109) in the bandgap reference module (101) and the intermediate frequency zero generation unit (105) in the LD0 circuit are adjusted in coordination to better optimize the intermediate frequency power supply rejection performance.

Abstract: An overshoot-free fast start-up bandgap reference circuit (100), a chip, and an electronic device. The bandgap reference circuit (100) comprises a bias current generating unit (101) and a reference core unit (102), wherein an output end of the bias current generating unit (101) is connected to an input end of the reference core unit (102), the bias current generating unit (101) generates a bias current (IBIAS) unrelated to the voltage of a power supply and having a zero temperature coefficient, the bias current (IBIAS) is an input signal of the reference core unit (102), and the reference core unit (102) generates a pre-charging current on the basis of the input bias current (IBIAS) and implements overshoot-free fast start-up by means of employing pre-charging.

Abstract: A power measurement circuit, a chip and a communication terminal. The power measurement circuit comprises a power measurement unit (100), a reference current generation unit (200), a voltage-current conversion unit (300) and an operation output unit (400), wherein an output end of the power measurement unit (100) is connected to an input end of the voltage-current conversion unit (300), and an output end of the voltage-current conversion unit (300) and an output end of the reference current generation unit (200) are respectively connected to an input end of the operation output unit (400). By means of the circuit, during the process of a power measurement unit (100) converting, into a direct-current voltage, a received radio frequency signal to be measured, sensitivity adjustment is performed, such that the measurement sensitivity can be effectively adjusted.

Abstract: An adaptive overshoot-voltage suppression circuit (100), a reference circuit, a chip and a communication terminal. The adaptive overshoot-voltage suppression circuit (100) comprises an overshoot-voltage suppression unit (1001) and a voltage-current conversion unit (1002), wherein an input end of the overshoot-voltage suppression unit (1001) is connected to a preset sampling point on a reference circuit to be tested, an output end of the overshoot-voltage suppression unit (1001) is connected to an input end of the voltage-current conversion unit (1002), and an output end of the voltage-current conversion unit (1002) is connected to a preset adjustment point on said reference circuit.

Abstract: The present invention provides a mRNA composition for microneedle administration and its application. The composition includes an aqueous phase solution and a lipid solution, wherein the lipid solution encapsulates the substance in the aqueous phase solution to form lipid nanoparticles (LNPs), and the aqueous phase solution includes mRNA encoding the corresponding protein and a buffer. It was found that an improved buffer pH could substantially increase the drug loading capacity of LNPs, and reduce the use level of composition and excipients and the dose for microneedle administration with less toxic side effects and better therapeutic effects, and the microneedle administration technology could achieve increased effective expression, decreased expression in the liver, and prolonged in vivo expression of mRNA composition, and increased antibody titer in response to low-dose mRNA in vivo. The present invention really realizes microneedle intradermal administration of mRNA composition.

Abstract: Disclosed in the present invention are a chip port state detection circuit, a chip, and a communication terminal. The chip port state detection circuit, by means of a port detection conversion circuit, converts the state of a port to be detected into a corresponding voltage and respectively outputs same to a first comparator and a second comparator, which, after comparing same with a corresponding input reference voltage, output a logic signal to a chip ID determination circuit to obtain a chip ID corresponding to the state of the chip port to be detected, in order to distinguish multiple identical chips.

Abstract: Disclosed in the present invention are a low-temperature coefficient ring oscillator, a chip, and a communication terminal. The low-temperature coefficient ring oscillator comprises a temperature tracking compensation circuit, an inverter oscillation circuit, and a buffer shaping circuit. The temperature characteristics of the impedance of a PMOS tube and an NMOS tube in an inverter in the inverter oscillation circuit are tracked and compensated for by means of the impedance, along with temperature change, of a PMOS tube and a NMOS tube connected by a diode.

Abstract: Disclosed in the present invention are a charge pump circuit, a chip, and a communication terminal. The charge pump circuit comprises a phase clock generation module, an acceleration response control module, and a plurality of sub charge pump modules. By generating a plurality of clock signals with a fixed phase difference by means of the phase clock generation module, correspondingly controlling the plurality of sub charge pump modules to generate output voltages, and by means of the acceleration response control module, measuring the output voltage of each sub charge pump module, and separately outputting a logic signal to the phase clock generation module and each sub charge pump module, the frequency of the clock signals outputted by the phase clock generation module is changed, and the charge and discharge time of a capacitor in each sub charge pump module is reduced.

Abstract: Disclosed are an on-chip RC oscillator, a chip, and a communication terminal. The on-chip RC oscillator comprises a stabilized voltage supply module, an RC core oscillator module, a frequency sampling and conversion module, and a frequency trimming module. By means of the frequency sampling and conversion module, the clock frequency of the oscillator is sampled and detected in real time, and the sampled clock frequency is converted into a voltage signal, and then analog-to-digital conversion is performed to obtain a corresponding digital code, so that when the clock frequency changes, the frequency trimming module circuit converts said digital code into a control signal; a voltage having a suitable temperature coefficient is outputted for the RC core oscillator; also, a zero temperature coefficient current of a suitable magnitude is outputted for the RC core oscillator module, so as to precisely calibrate the clock frequency.

Abstract: Disclosed are a self-adaptive fast-response LDO circuit and a chip thereof. Said circuit comprises a band gap reference circuit, an error amplifier, a power tube, a feedback resistor network, and a self-adaptive acceleration response circuit. The current of the power tube is mirrored by means of the self-adaptive acceleration response circuit, such that the tail current of a differential circuit in the error amplifier can accelerate charging and discharging adaptively according to load changes of the LDO circuit. In addition, before the LDO circuit is stably balanced, the characteristics of unbalanced states of two differential input ends of the error amplifier are used to perform fast charging and discharging on the tail current of the differential circuit and a gate electrode of the power tube in an extremely short time, such that the response time of the LDO circuit is greatly reduced.